公开(公告)号：US20220375882A1

公开(公告)日：2022-11-24

申请号：US17323194

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim

IPC: H01L23/64 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02 ,  H01L21/768 ,  H01F3/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20210391264A1

公开(公告)日：2021-12-16

申请号：US16902959

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen ,  Gang Duan ,  Jason M. Gamba ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Deepak Vasant Kulkarni ,  Ravindra Vijay Tanikella

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20250096143A1

公开(公告)日：2025-03-20

申请号：US18470668

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48

Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.

公开(公告)号：US12230564B2

公开(公告)日：2025-02-18

申请号：US17345912

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Valery Ouvarov-Bancalero ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

公开(公告)号：US20230317592A1

公开(公告)日：2023-10-05

申请号：US17711749

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Hamid R. Azimi ,  Sri Chaitra Jyotsna Chavali ,  Tarek A. Ibrahim ,  Wei-Lun K Jen ,  Rahul Manepalli ,  Kevin T. McCarthy

IPC: H01L23/498

CPC classification number: H01L23/49894 ,  H01L23/49822 ,  H01L23/49827

Abstract: In one embodiment, a package substrate includes a substrate core, buildup layers, and one or more conductive traces. The substrate core includes at least one dielectric layer with hollow glass fibers. The buildup layers include dielectric layers below and above the substrate core.

公开(公告)号：US20230187386A1

公开(公告)日：2023-06-15

申请号：US17550236

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  John S. Guzek ,  Hamid Azimi

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L24/16 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface, the second surface having a cavity; a first die at least partially nested in the cavity; an insulating material on the second surface of the substrate, the insulating material having a first surface and an opposing second surface, wherein the first surface of the insulating material is at the second surface of the substrate; a planar inductor embedded in the insulating material, the planar inductor including a thin film at least partially surrounding a conductive trace; and a second die, at the second surface of the insulating material, electrically coupled to the first die.

公开(公告)号：US20230134770A1

公开(公告)日：2023-05-04

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11640942B2

公开(公告)日：2023-05-02

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20230080454A1

公开(公告)日：2023-03-16

申请号：US17473694

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Brandon C. Marin ,  Debendra Mallik ,  Tarek A. Ibrahim ,  Jeremy Ecton ,  Omkar G. Karhade ,  Bharat Prasad Penmecha ,  Xiaoqian Li ,  Nitin A. Deshpande ,  Mitul Modi ,  Bai Nie

IPC: G02B6/12 ,  H01L23/48

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：US20220406512A1

公开(公告)日：2022-12-22

申请号：US17352952

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Xin Ning ,  Kyu-oh Lee ,  Brent Williams ,  Brandon C. Marin ,  Tarek A. Ibrahim ,  Krishna Bharath ,  Sai Vadlamani

IPC: H01F27/255 ,  H01F27/29 ,  H01F27/28 ,  H01F41/04 ,  H01F41/02

Abstract: Techniques and mechanisms for providing structures of a magnetic material based inductor. In an embodiment, an inductor comprises a body of a magnetic material, and a conductor which extends along a surface of the body. The body comprises a carrier material and magnetic filler particles distributed in the carrier material. A passivation material of the inductor is provided adjacent to the conductor and to surfaces of the filler particles. The conductor and the passivation material comprise different respective material compositions, wherein the passivation material comprises one of nickel, tin, copper, palladium, or gold. In another embodiment, the inductor is one of a plated through hole inductor type of a planar inductor type.