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公开(公告)号：US20190096462A1
公开(公告)日：2019-03-28
申请号：US15717023
申请日：2017-09-27
发明人： Jin Ping Han , Xiao Sun , Teng Yang
IPC分类号： G11C11/22 , H03K19/177
CPC分类号： G11C11/223 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2275 , G11C11/54 , G11C11/5621 , G11C11/5628 , G11C11/5657 , G11C11/5671 , G11C16/04 , G11C16/08 , G11C16/10 , H03K19/1776
摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.
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公开(公告)号：US20180012123A1
公开(公告)日：2018-01-11
申请号：US15202729
申请日：2016-07-06
发明人： Jin P. Han , Xiao Sun
IPC分类号： G06N3/063 , H01L27/092 , G06N3/04 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1033 , G06N3/049 , G06N3/0635 , H01L27/092 , H01L27/24
摘要： A synapse network device includes an array of field effect transistor (FET) devices having controllable channel resistance. Pre-neurons are coupled to the array to provide input pulses to the array on first terminals of the FET devices. Post-neurons are coupled to the array to receive outputs from the array on second terminals of the FET devices and provide feedback to the array on third terminals of the FET devices, wherein a state of the FET devices is indicated based upon signals applied to the FET devices.
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公开(公告)号：US11574694B2
公开(公告)日：2023-02-07
申请号：US16157848
申请日：2018-10-11
发明人： Effendi Leobandung , Tayfun Gokmen , Xiao Sun , Yulong Li , Malte Rasch
摘要： A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.
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公开(公告)号：US11494655B2
公开(公告)日：2022-11-08
申请号：US15836098
申请日：2017-12-08
发明人： Xiao Sun , Youngseok Kim , Chun-Chen Yeh
摘要： A computer-implemented method for training a random matrix network is presented. The method includes initializing a random matrix, inputting a plurality of first vectors into the random matrix, and outputting a plurality of second vectors from the random matrix to be fed back into the random matrix for training. The random matrix can include a plurality of two-terminal devices or a plurality of three-terminal devices or a film-based device.
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公开(公告)号：US11244999B2
公开(公告)日：2022-02-08
申请号：US16502783
申请日：2019-07-03
发明人： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC分类号： H01L49/02 , H01L27/11507 , H01L21/3213 , H01L21/02 , H01L21/283 , H01B3/10
摘要： Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
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公开(公告)号：US20210064372A1
公开(公告)日：2021-03-04
申请号：US16558536
申请日：2019-09-03
发明人： Xiao Sun , Chia-Yu Chen , Naigang Wang , Jungwook Choi , Kailash Gopalakrishnan
摘要： An apparatus includes a memory and a processor coupled to the memory. The processor includes first and second sets of arithmetic units having first and second precision for floating-point computations, the second precision being lower than the first precision. The processor is configured to obtain a machine learning model trained in the first precision, to utilize the second set of arithmetic units to perform inference on input data, to utilize the first set of arithmetic units to generate feedback for updating parameters of the second set of arithmetic units based on the inference performed on the input data by the second set of arithmetic units, to tune parameters of the second set of arithmetic units based at least in part on the feedback generated by the first set of arithmetic units, and to utilize the second set of arithmetic units with the tuned parameters to generate inference results.
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公开(公告)号：US20210019116A1
公开(公告)日：2021-01-21
申请号：US16515174
申请日：2019-07-18
发明人： Xiao Sun , Ankur Agrawal , Kailash Gopalakrishnan , Silvia Melitta Mueller , Kerstin Claudia Schelm
摘要： A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y′ by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y′ to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.
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公开(公告)号：US10686040B2
公开(公告)日：2020-06-16
申请号：US16395084
申请日：2019-04-25
发明人： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC分类号： H01L27/088 , H01L29/12 , H01L29/06 , H01L27/085 , H01L23/52 , H01L21/8234
摘要： Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
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29.发明申请公开(公告)号：US20200005848A1
公开(公告)日：2020-01-02
申请号：US16021575
申请日：2018-06-28
发明人： Martin M. Frank , Jin-Ping Han , Dennis M. Newns , Paul M. Solomon , Xiao Sun
摘要： A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
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公开(公告)号：US20190180185A1
公开(公告)日：2019-06-13
申请号：US15836098
申请日：2017-12-08
发明人： Xiao Sun , Youngseok Kim , Chun-Chen Yeh
摘要： A computer-implemented method for training a random matrix network is presented. The method includes initializing a random matrix, inputting a plurality of first vectors into the random matrix, and outputting a plurality of second vectors from the random matrix to be fed back into the random matrix for training. The random matrix can include a plurality of two-terminal devices or a plurality of three-terminal devices or a film-based device.
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