公开(公告)号：US4967243A

公开(公告)日：1990-10-30

申请号：US221482

申请日：1988-07-19

申请人： Bantval J. Baliga ,  Martin F. Schlecht

发明人： Bantval J. Baliga ,  Martin F. Schlecht

IPC分类号： H01L27/07 ,  H01L29/10 ,  H01L29/73 ,  H01L29/78

CPC分类号： H01L29/7806 ,  H01L27/0727 ,  H01L27/0766 ,  H01L29/7302

摘要： A power semiconductor device which comprises either a bipolar transistor or a MOSFET, incorporates an integral Schottky diode in antiparallel connection with the transistor for conducting reverse current through the power semiconductor device. By fabricating the diode to exhibit a lower turn-on voltage, than the P-N junction at the base and collector interface in the bipolar transistor, or at the base and drift layer interface in the MOSFET, the power semiconductor device, when in the reverse conduction mode, exhibits excellent reverse recovery characteristics and without forward voltage overshoot transients.

摘要翻译： 包括双极晶体管或MOSFET的功率半导体器件包括与晶体管反并联连接的积分肖特基二极管，用于通过功率半导体器件传导反向电流。 通过制造二极管以表现出比双极晶体管中的基极和集电极界面处的PN结，或MOSFET中的基极和漂移层界面处的较低导通电压，功率半导体器件处于反向导通 模式，具有优异的反向恢复特性，无正向电压过冲瞬变。

公开(公告)号：US4890143A

公开(公告)日：1989-12-26

申请号：US225320

申请日：1988-07-28

申请人： Bantval J. Baliga ,  Charles S. Korman

发明人： Bantval J. Baliga ,  Charles S. Korman

IPC分类号： H01L27/02 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0255

摘要： A self-protected MOS gated device includes a PN junction disposed in an electrical path between the source electrode and the gate contact of the device and integrally formed with a DMOS cell of the device to protect the DMOS cell from surge voltages. The PN junction has conductivity characteristics selected to provide junction breakdown at a predetermined voltage level and at a predetermined location along the junction.

摘要翻译： 自保护MOS门控器件包括PN结，其设置在器件的源电极和栅极触点之间的电气路径中，并与器件的DMOS单元整体形成，以保护DMOS电池免受浪涌电压的影响。 PN结具有选择的导电特性，以在预定电压电平和沿着结的预定位置处提供结击穿。

公开(公告)号：US4799095A

公开(公告)日：1989-01-17

申请号：US69806

申请日：1987-07-06

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/423 ,  H01L29/74 ,  H01L29/745 ,  H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/42312 ,  H01L29/7404 ,  H01L29/7455

摘要： An MOS gate turn-off thyristor structure includes non-regenerative (three-layer or transistor) portions interspersed with the four-layer regenerative (thyristor) portions and further includes gate electrode segments disposed adjacent to relatively narrow portions of the base region. Upon application of an appropriate turn-off gate bias to the gate electrode segments, the base region of the regenerative portion in which they are disposed is pinched off and the current flowing therethrough is diverted to flow through the non-regenerative portion of the structure. This interrupts regeneration in the regenerative structure and the device turns off.

摘要翻译： MOS栅极截止晶闸管结构包括散布有四层再生（晶闸管）部分的非再生（三层或三极管）部分，并且还包括邻近基极区域的较窄部分设置的栅电极段。 当向栅极电极段施加适当的截止栅极偏压时，将其设置在其中的再生部分的基极区域夹断，并且流过其中的电流被转向流过结构的非再生部分。 这会中断再生结构中的再生，器件关闭。

公开(公告)号：US4743952A

公开(公告)日：1988-05-10

申请号：US482075

申请日：1983-04-04

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7395 ,  H01L29/7802

摘要： An insulated-gate semiconductor device includes an IGFET with channel, base, drift and drain regions, and further includes source and drain electrodes attached to at least the base region and to the drain region, repectively. The device further includes a carrier injection region which adjoins the IGFET drift region and forms a P-N junction therewith. Biasing structure connected to the carrier injection region and effective during the on-state of the device is provided for forward biasing the P-N junction by an amount sufficient to induce injection of carriers from the carrier injection region, across the P-N junction, and into the IGFET drift region. As a consequence, the on-resistance of the device is markedly reduced.

摘要翻译： 绝缘栅半导体器件包括具有沟道，基极，漂移和漏极区域的IGFET，并且还包括分别连接到至少基极区域和漏极区域的源极和漏极电极。 该装置还包括邻接IGFET漂移区并与其形成P-N结的载流子注入区。 提供连接到载流子注入区域并且在器件的导通状态期间有效的偏置结构用于将PN结向前偏置足以引起来自载流子注入区域的载流子穿过PN结并且进入IGFET的量 漂移区。 因此，器件的导通电阻显着降低。

公开(公告)号：US4641174A

公开(公告)日：1987-02-03

申请号：US510520

申请日：1983-08-08

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/47 ,  H01L29/808 ,  H01L29/812 ,  H01L29/861 ,  H01L29/872 ,  H01L29/12

CPC分类号： H01L29/872 ,  H01L29/861 ,  H01L29/8083 ,  H01L29/8122

摘要： A high speed semiconductor pinch rectifier attains low forward voltage drop and low reverse leakage current by utilizing depletion region pinch-off of conduction channels in a high-resistivity region. In a preferred form, the pinch rectifier additionally utilizes a Schottky barrier contact so as to facilitate device fabrication.

摘要翻译： 高速半导体夹点整流器通过利用高电阻率区域中的导通通道的耗尽区夹断来实现低正向压降和低反向漏电流。 在优选形式中，夹紧整流器另外使用肖特基势垒接触，以便于器件制造。

公开(公告)号：US4569118A

公开(公告)日：1986-02-11

申请号：US630473

申请日：1984-07-11

申请人： Bantval J. Baliga ,  Bruce W. Wessels

发明人： Bantval J. Baliga ,  Bruce W. Wessels

IPC分类号： H01L21/205 ,  H01L21/306 ,  H01L29/10 ,  H01L29/739 ,  H01L29/747

CPC分类号： H01L21/30608 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1012 ,  H01L29/7392 ,  Y10S148/05

摘要： Gate turn-off field controlled thyristors having high forward blocking capabilities and high blocking gains, and planar, junction gate field effect transistors having high source-to-drain breakdown voltage capability with high differential blocking gain, include a gate region having a plurality of vertical-walled grooves. The devices are fabricated by preferentially etching one surface of a semiconductor substrate, selectively refilling the grooves with a vapor phase epitaxial growth, forming a plurality of first electrode regions on the same surface and interdigitated with the gate region, and forming a second electrode region on the opposite surface of the substrate.

摘要翻译： 具有高正向阻断能力和高阻塞增益的栅极截止场控制晶闸​​管，具有高差分阻塞增益的高源极 - 漏极击穿电压能力的平面结结栅场效应晶体管包括具有多个垂直 壁槽。 通过优先蚀刻半导体衬底的一个表面，通过气相外延生长选择性地重新填充沟槽来制造器件，在同一表面上形成多个第一电极区域并与栅极区域交错，并且形成第二电极区域 衬底的相对表面。

公开(公告)号：US4523111A

公开(公告)日：1985-06-11

申请号：US473089

申请日：1983-03-07

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H03K17/06 ,  H03K17/687 ,  H03K17/60 ,  H03K3/353

CPC分类号： H03K17/06 ,  H03K17/6871

摘要： An electrical circuit includes a JFET serially connected to an IGFET, the gate of the IGFET constituting the gate for the circuit. Biasing structure, such as a resistor, is connected between the circuit gate and the gate of the JFET for forward-biasing the P-N junction of the JFET extant between its gate and channel regions. When this P-N junction is biased by more than about 0.6 volts for a silicon JFET, the JFET gate region injects current carriers into the JFET channel region, whereby bipolar conduction occurs in the JFET channel region and low on-resistance for the circuit is achieved. In a preferred circuit the biasing structure comprises an IGFET, which advantageously results in the circuit gate having a high input impedance.

摘要翻译： 电路包括串联连接到IGFET的JFET，IGFET的栅极构成电路的栅极。 诸如电阻器的偏置结构连接在电路栅极和JFET的栅极之间，用于在其栅极和沟道区域之间正向偏置JFET存在器的P-N结。 当这种P-N结对于硅JFET被偏置大于约0.6伏特时，JFET栅极区域将电流载流子注入到JFET沟道区域中，由此在JFET沟道区域中发生双极导通，并实现了电路的低导通电阻。 在优选电路中，偏置结构包括IGFET，其有利地导致电路栅极具有高输入阻抗。

公开(公告)号：US4128440A

公开(公告)日：1978-12-05

申请号：US899118

申请日：1978-04-24

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： C30B19/00 ,  C30B29/06 ,  H01L21/208 ,  H01L21/74

CPC分类号： H01L21/74 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02625 ,  H01L21/02628

摘要： Buried regions of predetermined conductivity in silicon semiconductor devices are formed with substantially no out diffusion from the substrate and buried region, and with substantially no lateral autodoping, by diffusing the region into a monocrystalline silicon wafer doped to one conductivity type, and depositing silicon from a melt supersaturated with silicon and containing conductivity type determining impurities, epitaxially atop the wafer. The device is completed by performing conventional diffusion of conductivity type determining impurities into the epitaxially deposited layer.

摘要翻译： 通过将该区域扩散到掺杂到一种导电类型的单晶硅晶片中，并且从一个导电类型淀积硅来形成硅半导体器件中具有预定导电性的掩埋区域，其基本上没有从衬底和掩埋区域的扩散，并且基本上没有横向自动掺杂 熔融过硅，并含有导电型确定杂质，外延在晶圆顶上。 通过将导电类型确定杂质常规扩散到外延沉积层中来完成该器件。

公开(公告)号：US5635412A

公开(公告)日：1997-06-03

申请号：US467174

申请日：1995-06-06

申请人： Bantval J. Baliga ,  Dev Alok

发明人： Bantval J. Baliga ,  Dev Alok

IPC分类号： H01L21/04 ,  H01L21/265 ,  H01L21/329 ,  H01L29/06 ,  H01L29/24 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L21/266

CPC分类号： H01L29/1608 ,  H01L29/6606 ,  H01L29/861 ,  H01L29/872 ,  Y10S438/931

摘要： Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.

摘要翻译： 耐压击穿的单晶碳化硅半导体器件通过在单晶碳化硅衬底的表面上形成与碳化硅器件相邻并围绕的非晶碳化硅终止区来获得。 优选通过以足够的能量和剂量将电惰性离子（例如氩）注入到衬底面中来形成无定形终止区域以使衬底面非晶化。 器件触点或触点用作注入掩模，以为器件提供自对准的端接区域。 端接器件可能具有接近碳化硅理想值的耐电压击穿电阻。

公开(公告)号：US5612567A

公开(公告)日：1997-03-18

申请号：US645231

申请日：1996-05-13

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L27/095 ,  H01L29/00 ,  H01L29/93

CPC分类号： H01L29/8725 ,  H01L29/872

摘要： A Schottky rectifier includes MOS-filled trenches and an anode electrode at a face of a semiconductor substrate and an optimally nonuniformly doped drift region therein which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage drop. The nonuniformly doped drift region contains a concentration of first conductivity type dopants therein which increases monotonically in a direction away from a Schottky rectifying junction formed between the anode electrode and the drift region. A profile of the doping concentration in the drift region is preferably a linear or step graded profile with a concentration of less than about 5.times.10.sup.16 cm.sup.-3 (e.g., 1.times.10.sup.16 cm.sup.-3) at the Schottky rectifying junction and a concentration of about ten times greater (e.g., 3.times.10.sup.17 cm.sup.-3) at a junction between the drift region and a cathode region. The thickness of the insulating regions (e.g., SiO.sub.2) in the MOS-filled trenches is also greater than about 1000 .ANG. to simultaneously inhibit field crowding and increase the breakdown voltage of the device. The nonuniformly doped drift region is preferably formed by epitaxial growth from the cathode region and doped in-situ.

摘要翻译： 肖特基整流器包括MOS填充沟槽和在半导体衬底的表面处的阳极电极和在其中的最佳不均匀掺杂漂移区域，其组合提供具有低反向偏置漏电流和低正向压降的高阻断电压能力。 不均匀掺杂的漂移区域包含其中在远离形成在阳极电极和漂移区域之间的肖特基整流结的方向上单调增加的第一导电类型掺杂剂的浓度。 在漂移区中掺杂浓度的曲线优选是在肖特基整流结处具有小于约5×10 16 cm -3（例如，1×10 16 cm -3）的浓度的线性或阶梯分布轮廓，并且浓度为约十倍 （例如，3×10 17 cm -3）在漂移区域和阴极区域之间的连接处。 MOS填充的沟槽中的绝缘区域（例如，SiO 2）的厚度也大于约1000，以同时抑制场强拥挤并增加器件的击穿电压。 非均匀掺杂漂移区优选通过从阴极区域外延生长并原位掺杂形成。