公开(公告)号：US09754785B2

公开(公告)日：2017-09-05

申请号：US14993141

申请日：2016-01-12

申请人： Eun-Jung Kim ,  Sung-Un Kwon ,  Yong-Kwan Kim ,  Yoo-Sang Hwang ,  Young-Sik Seo

发明人： Eun-Jung Kim ,  Sung-Un Kwon ,  Yong-Kwan Kim ,  Yoo-Sang Hwang ,  Young-Sik Seo

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108

CPC分类号： H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885

摘要： In a method of manufacturing a semiconductor device, sacrificial layer patterns extending in a first direction are formed on an etch target layer. Preliminary mask patterns are formed on opposite sidewall surfaces of each of the sacrificial layer patterns. A filling layer is formed to fill a space between the preliminary mask patterns. Upper portions of the preliminary mask patterns are etched to form a plurality of mask patterns. Each of the mask patterns is symmetric with respect to a plane passing a center point of each of the mask patterns in a second direction substantially perpendicular to the first direction and extending in the first direction. The sacrificial layer patterns and the filling layer are removed. The etch target layer is etched using the mask patterns as an etching mask to form a plurality of target layer patterns.

公开(公告)号：US20160027787A1

公开(公告)日：2016-01-28

申请号：US14847324

申请日：2015-09-08

申请人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

发明人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

IPC分类号： H01L27/108 ,  H01L21/3213

CPC分类号： H01L27/10855 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.

摘要翻译： 电子器件可以包括衬底和衬底上的多个间隔开的衬垫。 每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。 还讨论了相关方法，设备和结构。

公开(公告)号：US08742493B2

公开(公告)日：2014-06-03

申请号：US13285263

申请日：2011-10-31

申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

IPC分类号： H01L27/108

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

公开(公告)号：US20120299090A1

公开(公告)日：2012-11-29

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L29/78

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US07601630B2

公开(公告)日：2009-10-13

申请号：US11020827

申请日：2004-12-22

申请人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

IPC分类号： H01L21/4763 ,  H01L21/8239 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

摘要翻译： 制造半导体存储器件的方法和形成电阻器和蚀刻保护层的结构以降低接触电阻。 根据本发明的制造半导体存储器件的方法包括在具有单元阵列区域，芯区域和周边区域的半导体衬底上形成绝缘层，每个晶体管阵列区域和外围区域都具有形成在其中的至少一个晶体管，并且形成第一 在绝缘层上的芯区域中的着陆焊盘和外围区域中的第二着陆焊盘，第一着陆焊盘与第一导电线的一部分重叠。 本发明通过简化的过程降低了接触电阻并且防止或最小化由不对准引起的设备故障。

公开(公告)号：US20070259494A1

公开(公告)日：2007-11-08

申请号：US11780026

申请日：2007-07-19

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/8234 ,  H01L21/4763

CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US06977197B2

公开(公告)日：2005-12-20

申请号：US10884040

申请日：2004-07-02

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

摘要： The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact plugs filling in the upper and lower contact holes.

摘要翻译： 本发明公开了一种半导体器件，包括：形成在半导体衬底上的位线着色焊盘; 存储着陆垫形成在位线着陆垫的两侧; 形成在具有着色焊盘的半导体衬底的整个表面上的位线层间绝缘体; 布置在位线层间绝缘体上的多个并行位线图案; 填充在位线图案之间的栅极区域中的位线绝缘层图案; 形成在位线绝缘层图案中的上接触孔暴露位线图案的侧壁并且位于比位线图案的上表面高; 覆盖上接触孔的侧壁的接触孔间隔件; 穿过位线绝缘层图案的下接触孔和由接触孔间隔件包围的孔下方的位线层间绝缘体暴露存储节点着陆焊盘并与上接触孔自称; 以及填充上，下接触孔的存储节点接触塞。

公开(公告)号：US06927126B2

公开(公告)日：2005-08-09

申请号：US10830941

申请日：2004-04-22

申请人： Je-Min Park ,  Seung-young Son ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Seung-young Son ,  Yoo-Sang Hwang

IPC分类号： H01L21/28 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A second insulating layer is formed on a first insulating layer. A plurality of stacks each including a bit line and a bit line mask are formed on the second insulating layer. A third insulating layer is formed overlying the second insulating layer to fill gaps between the plurality of stacks. A hard mask layer is formed on the third insulating layer. A photoresist pattern is formed on the hard mask layer. The photoresist pattern has an opening region that intersects the plurality of stacks. The hard mask layer and the third insulating layer are sequentially etched, using the photoresist pattern as an etching mask, thereby forming a hard mask pattern and forming a recess in the third insulating layer. The recess exposes a portion of upper sidewalls of the bit line mask. Spacers are formed on the exposed upper sidewalls of the bit line mask.

摘要翻译： 在第一绝缘层上形成第二绝缘层。 在第二绝缘层上形成各自包括位线和位线掩模的堆叠。 在第二绝缘层上形成第三绝缘层以填充多个堆叠之间的间隙。 在第三绝缘层上形成硬掩模层。 在硬掩模层上形成光刻胶图形。 光致抗蚀剂图案具有与多个堆叠相交的开口区域。 使用光致抗蚀剂图案作为蚀刻掩模，依次蚀刻硬掩模层和第三绝缘层，从而形成硬掩模图案并在第三绝缘层中形成凹部。 凹口露出位线掩模的上侧壁的一部分。 间隔件形成在位线掩模的暴露的上侧壁上。

公开(公告)号：US06288446B1

公开(公告)日：2001-09-11

申请号：US09790642

申请日：2001-02-23

申请人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01G706

摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

公开(公告)号：US06218296B1

公开(公告)日：2001-04-17

申请号：US09346922

申请日：1999-07-02

申请人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01L2144

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/90

摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

摘要翻译： 一种半导体器件和制造具有与高介电膜兼容的柱状电容器存储节点的半导体器件的方法，其中柱状电容器存储节点包括易于蚀刻的厚导电金属层和完全薄的导电层 涂覆厚的导电金属层。 薄导电层在随后的高介电沉积和退火和各种氧化过程期间保护厚的导电金属层。