公开(公告)号：US20060118813A1

公开(公告)日：2006-06-08

申请号：US11337143

申请日：2006-01-20

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/111

CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

摘要翻译： 横向JFET具有包括由n型杂质区形成的n型半导体层（3）和在n型半导体层（3）上由p型杂质区形成的p型半导体层的基本结构， 。 此外，在p型半导体层中，设置延伸到n型半导体层（3）中并含有杂质的p型杂质的p +型栅极区域层（7） 浓度高于n型半导体层（3）的浓度以及与p + +型栅极区域层间隔开的n + + +型漏极区域（9） （7）预定距离并且包含杂质浓度高于n型半导体层（3）的杂质浓度的n型杂质。 利用这种结构，可以提供横向JFET，其具有进一步降低的导通电阻，同时保持高的击穿电压性能。

公开(公告)号：US20060033554A1

公开(公告)日：2006-02-16

申请号：US11234379

申请日：2005-09-26

申请人： Hiroyuki Matsunami ,  Kouji Okada ,  Takaaki Ido

发明人： Hiroyuki Matsunami ,  Kouji Okada ,  Takaaki Ido

IPC分类号： G05F1/10

CPC分类号： H03L7/0898 ,  H03L7/0895 ,  H03L7/18

摘要： A charge pump circuit is disclosed in which a spike-shaped noise (glitch) generated in an output is reduced. The charge pump circuit comprises: a first transistor, one of the terminals of which is connected to a high electric potential power source, turned on and off according to a charge-up signal; a second transistor, one of the terminals of which is connected to a low electric potential power source, turned on and off according to a charge-down signal; a first current restricting element connected between the other terminal of the first transistor and the output of a charge pump; and a second current restricting element connected between the other terminal of the second transistor and the output of the charge pump.

摘要翻译： 公开了一种电荷泵电路，其中在输出中产生的尖状噪声（毛刺）减小。 电荷泵电路包括：第一晶体管，其一端连接到高电位电源，根据充电信号导通和截止; 第二晶体管，其一端连接到低电位电源，根据降压信号导通和截止; 连接在第一晶体管的另一个端子和电荷泵的输出端之间的第一电流限制元件; 以及连接在第二晶体管的另一端和电荷泵的输出之间的第二电流限制元件。

公开(公告)号：US20050275471A1

公开(公告)日：2005-12-15

申请号：US10968005

申请日：2004-10-20

申请人： Hiroyuki Matsunami

发明人： Hiroyuki Matsunami

IPC分类号： G06F1/04 ,  H03L7/00 ,  H03L7/18 ,  H04L7/033

CPC分类号： H03L7/18

摘要： To present a clock generator capable of spreading the spectrum of oscillation frequency by simple control in a small additional circuit, and its control method. A phase locked loop circuit is provided from a frequency phase comparator 11, an output clock signal PO is outputted from a voltage control oscillator (VCO) 14 by way of a charge pump circuit (CP) 12 and a loop filter (LF) 13, and is returned to the frequency phase comparator 11 by way of a frequency divider (DIV) 15. Detecting the phase difference of reference clock signal R and divided clock signal D, and locking the oscillation frequency of the output clock signal PO to specified frequency, a modulation signal M is outputted from a modulation pulse generator 1 regardless of phase locked control of phase locked loop circuit, and is superposed on phase comparison signal P, and thereby the oscillation frequency of output clock signal PO is modulated. An output clock signal PO having a predetermined spectrum spread characteristic can be obtained.

摘要翻译： 提出能够通过在小额外电路中简单控制来扩展振荡频率频谱的时钟发生器及其控制方法。 从频率相位比较器11提供锁相环电路，通过电荷泵电路（CP）12和环路滤波器（LF）13从压控振荡器（VCO）14输出输出时钟信号PO， 并通过分频器（DIV）15返回到频率相位比较器11。 检测参考时钟信号R和分频时钟信号D的相位差，并将输出时钟信号PO的振荡频率锁定到指定频率，调制信号M从调制脉冲发生器1输出，不管锁相控制 并且叠加在相位比较信号P上，从而调制输出时钟信号PO的振荡频率。 可以获得具有预定频谱扩展特性的输出时钟信号PO。

公开(公告)号：US06734461B1

公开(公告)日：2004-05-11

申请号：US10070472

申请日：2002-03-07

申请人： Hiromu Shiomi ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami

发明人： Hiromu Shiomi ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami

IPC分类号： H01L310312

CPC分类号： H01L29/1608 ,  C30B23/00 ,  C30B23/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02516 ,  H01L21/02529 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/78

摘要： A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

摘要翻译： SiC晶片包括其中晶体取向基本上为{03-38}的4H多型SiC衬底2，以及由该SiC衬底2上形成的由SiC构成的缓冲层4. {03-38}面形成 相对于其中微孔等的<0001>轴向延伸大约35°，因此在晶体侧消除了微管等，并且不会穿过缓冲层4上的有源层6。晶格不匹配 在SiC衬底2和有源层6之间被缓冲层4抑制。此外，由于使用4H多型，电子迁移率的各向异性低。 因此，可以获得在电子迁移率中几何异向性小的SiC晶片和SiC半导体器件，并且可以减小由晶格失配引起的应变以及其制造方法。

公开(公告)号：US08513938B2

公开(公告)日：2013-08-20

申请号：US13316522

申请日：2011-12-11

申请人： Suguru Tachibana ,  Hiroyuki Matsunami ,  Yukinobu Tanida

发明人： Suguru Tachibana ,  Hiroyuki Matsunami ,  Yukinobu Tanida

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： G05F3/30

摘要： A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.

摘要翻译： 参考电压电路包括第一放大器，第一负载装置和第一PN结装置，第二和第三负载装置和第二PN结装置，偏移电压降低电路，耦合节点势能取出电路和区域调整电路 。 偏移电压降低电路被配置为减少第一放大器处的第一和第二输入端之间的偏移电压，并且耦合节点电势取出电路被配置为取出第一和第二耦合节点的电位。 区域调整电路被配置为根据由耦合节点电势取出电路取出的第一和第二耦合节点的电位来调整第二PN结装置的面积。

公开(公告)号：USRE43840E1

公开(公告)日：2012-12-04

申请号：US12926030

申请日：2010-10-21

申请人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/0312

CPC分类号： H01L29/66068 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/8083

摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.

摘要翻译： 碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。 在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。 在沟槽的内表面上形成SiC外延层。

公开(公告)号：US07834673B2

公开(公告)日：2010-11-16

申请号：US12342780

申请日：2008-12-23

申请人： Hiroyuki Matsunami

发明人： Hiroyuki Matsunami

IPC分类号： H03H11/26

CPC分类号： H03K7/08 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00058

摘要： A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal.

摘要翻译： 一种可变延迟电路，包括被配置为延迟输入信号的第一延迟元件，并联耦合到第一延迟元件的第二延迟元件，并且还被配置为延迟输入信号;控制电流供应部分，被配置为提供控制电流， 第一延迟元件的延迟量和第二延迟元件的延迟量，以及输出信号选择部分，被配置为根据选择从第一延迟元件输出的输出信号和来自第二延迟元件的输出信号中的任何一个 用于选择输入信号的延迟时间的信号。

公开(公告)号：US20090315082A1

公开(公告)日：2009-12-24

申请号：US12552212

申请日：2009-09-01

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源极/漏极区之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US20060202238A1

公开(公告)日：2006-09-14

申请号：US11402701

申请日：2006-04-11

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

公开(公告)号：US20050057241A1

公开(公告)日：2005-03-17

申请号：US10792810

申请日：2004-03-05

申请人： Yasukazu Ono ,  Koji Okada ,  Hiroyuki Matsunami

发明人： Yasukazu Ono ,  Koji Okada ,  Hiroyuki Matsunami

IPC分类号： G01R23/165 ,  G01R19/00 ,  G01R23/00 ,  G01R31/28

CPC分类号： G01R31/2824 ,  G01R19/0007

摘要： An object of this invention is to provide a band distribution inspecting device and band distribution inspecting method capable of carrying out inspection on whether or not a scattered oscillation signal oscillated containing a frequency variation from the fundamental frequency with the fundamental frequency as a reference point has a band distribution rapidly, with a simple way and at a cheap price. A scattered oscillation signal SSS inputted to a band distribution detecting section 22 is outputted as a predetermined band pass signal SBP through a band pass filter 17 having a predetermined pass band of a predetermined narrow-band width Δf within a band distribution. This signal is converted to a root-mean-square value by a smoother 19, smoothed by a capacitor C1 and transferred to a general purpose inspecting device 21 as a DC signal SAV. The DC signal SAV is compared with a predetermined voltage value VX by a comparator 25 and its comparison result is judged by a judging section 25 and then, an inspection result is outputted as a judging signal J. As a result, an edge frequency in the band distribution of the scattered oscillation signal SSS and disturbance of frequency variation within/out of the band and dullness in waveform and the like can be inspected for.

摘要翻译： 本发明的目的是提供一种能够对以基频为基准的包含来自基频的频率变化的振荡信号是否具有振荡的频带分布检查装置和频带分布检查方法进行检查 乐队分布迅速，以简单的方式和便宜的价格。 输入到频带分布检测部分22的散射振荡信号SSS作为预定的带通信号SBP通过具有预定窄带宽度Deltaf的预定通带的带通滤波器17输出。 该信号由平滑器19转换成均方根值，由电容器C1平滑，并作为DC信号SAV传送到通用检测装置21。 通过比较器25将DC信号SAV与预定的电压值VX进行比较，并且判断部25判断其比较结果，然后作为判断信号J输出检查结果。结果，边缘频率 可以检查散射振荡信号SSS的频带分布和波段内/频带内的频率变化的干扰以及波形等中的钝度。