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公开(公告)号：US11562792B2
公开(公告)日：2023-01-24
申请号：US17184991
申请日：2021-02-25
Applicant: KIOXIA CORPORATION
Inventor： Riki Suzuki , Yoshihisa Kojima
Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.
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公开(公告)号：US11416169B2
公开(公告)日：2022-08-16
申请号：US17199586
申请日：2021-03-12
Applicant: Kioxia Corporation
Inventor： Yoshihisa Kojima , Riki Suzuki
Abstract: A memory system includes a controller that transmits, to a memory chip, one first command set indicating a head of a third storage area being one of second storage areas, in a case where first data is read to a first buffer of the memory chip. The first data includes a plurality of first data segments having been stored in the second storage areas. The memory chip includes circuitry that outputs a second data segment and a third data segment to the controller in a period after the controller transmits the first command set to the memory chip before the controller transmits a second command set to the memory chip. The second data segment is a data segment having been stored in the third storage area. The third data segment is a data segment having been stored in a fourth storage area different from the third storage area.
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公开(公告)号：US11342026B2
公开(公告)日：2022-05-24
申请号：US17018147
申请日：2020-09-11
Applicant: Kioxia Corporation
Inventor： Suguru Nishikawa , Takehiko Amaki , Yoshihisa Kojima , Shunichi Igahara
Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
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公开(公告)号：US11238936B2
公开(公告)日：2022-02-01
申请号：US17014677
申请日：2020-09-08
Applicant: KIOXIA CORPORATION
Inventor： Masanobu Shirakawa , Marie Takada , Tsukasa Tokutomi , Yoshihisa Kojima , Kiichi Tachi
IPC: G11C16/04 , G11C16/08 , G11C16/34 , H01L27/1157 , G11C16/12 , G11C16/26 , G11C11/56 , H01L27/11582 , G11C16/10
Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
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公开(公告)号：US11194656B2
公开(公告)日：2021-12-07
申请号：US16774609
申请日：2020-01-28
Applicant: KIOXIA CORPORATION
Inventor： Shunichi Igahara , Yoshihisa Kojima , Takehiko Amaki , Suguru Nishikawa
Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.
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Patent Agency Ranking
公开(公告)号：US12170118B2
公开(公告)日：2024-12-17
申请号：US18088129
申请日：2022-12-23
Applicant: Kioxia Corporation
Inventor： Yoshihisa Kojima , Shunichi Igahara , Toshikatsu Hida
Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a first block that includes first and second sub-blocks. The memory controller instructs the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory. In response to a first value corresponding to the first sub-block having reached a first threshold value, the memory controller reads first data from the first sub-block, executes an error correction process on the first data read from the first sub-block, and writes the first data on which the error correction process has been executed into the non-volatile memory.
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公开(公告)号：US12046300B2
公开(公告)日：2024-07-23
申请号：US18459501
申请日：2023-09-01
Applicant: KIOXIA CORPORATION
Inventor： Tomoya Kamata , Yoshihisa Kojima , Suguru Nishikawa
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.
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公开(公告)号：US12033705B2
公开(公告)日：2024-07-09
申请号：US18365929
申请日：2023-08-04
Applicant: Kioxia Corporation
Inventor： Yoshihisa Kojima
CPC classification number: G11C16/32 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3495 , G11C2211/5648
Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
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公开(公告)号：US11954357B2
公开(公告)日：2024-04-09
申请号：US17468895
申请日：2021-09-08
Applicant: Kioxia Corporation
Inventor： Takehiko Amaki , Shunichi Igahara , Toshikatsu Hida , Yoshihisa Kojima , Riki Suzuki
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0638 , G06F3/064 , G06F3/0679
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.
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公开(公告)号：US11749350B2
公开(公告)日：2023-09-05
申请号：US18089695
申请日：2022-12-28
Applicant: Kioxia Corporation
Inventor： Suguru Nishikawa , Takehiko Amaki , Yoshihisa Kojima , Shunichi Igahara
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/26 , G11C16/3459
Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
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