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    SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER
    21.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER 有权

    公开(公告)号：US20230032500A1

    公开(公告)日：2023-02-02

    申请号：US17962302

    申请日：2022-10-07

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi MAEJIMA

    IPC: G11C16/10 ,  G11C16/16 ,  G06F12/02 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F3/06

    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

    MEMORY SYSTEM, MEMORY CONTROLLER, AND SEMICONDUCTOR MEMORY DEVICE
    22.
    发明申请
    MEMORY SYSTEM, MEMORY CONTROLLER, AND SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220027094A1

    公开(公告)日：2022-01-27

    申请号：US17494015

    申请日：2021-10-05

    Applicant: Kioxia Corporation

    Inventor： Hiroshi MAEJIMA

    IPC: G06F3/06 ,  G11C16/08 ,  G06N3/08 ,  G11C16/04

    Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

    MEMORY DEVICE WITH MEMORY PILLAR INSIDE CONDUCTOR
    23.
    发明申请
    MEMORY DEVICE WITH MEMORY PILLAR INSIDE CONDUCTOR 有权

    公开(公告)号：US20250054524A1

    公开(公告)日：2025-02-13

    申请号：US18921736

    申请日：2024-10-21

    Applicant: Kioxia Corporation

    Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO

    IPC: G11C7/10 ,  G11C7/08 ,  G11C16/16

    Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

    SEMICONDUCTOR STORAGE DEVICE
    24.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20240096417A1

    公开(公告)日：2024-03-21

    申请号：US18337605

    申请日：2023-06-20

    Applicant: Kioxia Corporation

    Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Keita KIMURA

    IPC: G11C16/04 ,  G11C5/06 ,  G11C16/14 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/14 ,  G11C16/26

    Abstract: In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.

    SEMICONDUCTOR STORAGE DEVICE
    28.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20220122666A1

    公开(公告)日：2022-04-21

    申请号：US17565241

    申请日：2021-12-29

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi MAEJIMA

    IPC: G11C16/04 ,  G11C5/06 ,  G11C7/06 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

    Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

    MEMORY DEVICE TO EXECUTE READ OPERATION USING READ TARGET VOLTAGE
    29.
    发明申请
    MEMORY DEVICE TO EXECUTE READ OPERATION USING READ TARGET VOLTAGE 有权

    公开(公告)号：US20210343350A1

    公开(公告)日：2021-11-04

    申请号：US17377857

    申请日：2021-07-16

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi MAEJIMA

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

    Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

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