公开(公告)号：US08351244B2

公开(公告)日：2013-01-08

申请号：US13001695

申请日：2010-05-28

申请人： Takashi Okada ,  Takumi Mikawa ,  Koji Arita

发明人： Takashi Okada ,  Takumi Mikawa ,  Koji Arita

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14). The method includes: forming a first interlayer insulating film (3); forming a contact hole in the interlayer insulating film (3); depositing a first plug material (4) in the contact hole and on the first interlayer insulating film (3); performing a first polishing in which the first plug material (4) is polished until the first interlayer insulating film (3) is exposed; depositing a conductive film (6a) that becomes a first electrode (6) of the current steering element (10), on the first plug material (4) and the first interlayer insulating film (3) after the first polishing; and performing a second polishing in which a surface of the conductive film (6a) is polished.

摘要翻译： 一种制造存储单元阵列的方法，其中第一导电层（2）和第二导电层（14）在半导体衬底（1）上方延伸并且彼此三维交叉，并且每个存储单元包括电流转向 在第一导电层（2）和第二导电层（14）之间的三维交叉点中的相应一个处提供元件（10）和彼此串联电连接的可变电阻元件（23）。 该方法包括：形成第一层间绝缘膜（3）; 在层间绝缘膜（3）中形成接触孔; 在所述接触孔和所述第一层间绝缘膜（3）上沉积第一插塞材料（4）; 执行抛光所述第一插塞材料（4）直到所述第一层间绝缘膜（3）露出的第一抛光; 在第一次抛光之后，在第一插头材料（4）和第一层间绝缘膜（3）上沉积成为当前操舵元件（10）的第一电极（6）的导电膜（6a） 并进行抛光导电膜（6a）的表面的第二研磨。

公开(公告)号：US20110103133A1

公开(公告)日：2011-05-05

申请号：US13001695

申请日：2010-05-28

申请人： Takashi Okada ,  Takumi Mikawa ,  Koji Arita

发明人： Takashi Okada ,  Takumi Mikawa ,  Koji Arita

IPC分类号： G11C11/00 ,  H01L45/00 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14). The method includes: forming a first interlayer insulating film (3); forming a contact hole in the interlayer insulating film (3); depositing a first plug material (4) in the contact hole and on the first interlayer insulating film (3); performing a first polishing in which the first plug material (4) is polished until the first interlayer insulating film (3) is exposed; depositing a conductive film (6a) that becomes a first electrode (6) of the current steering element (10), on the first plug material (4) and the first interlayer insulating film (3) after the first polishing; and performing a second polishing in which a surface of the conductive film (6a) is polished.

摘要翻译： 一种制造存储单元阵列的方法，其中第一导电层（2）和第二导电层（14）在半导体衬底（1）上方延伸并且彼此三维交叉，并且每个存储单元包括电流转向 在第一导电层（2）和第二导电层（14）之间的三维交叉点中的相应一个处提供元件（10）和彼此串联电连接的可变电阻元件（23）。 该方法包括：形成第一层间绝缘膜（3）; 在层间绝缘膜（3）中形成接触孔; 在所述接触孔和所述第一层间绝缘膜（3）上沉积第一插塞材料（4）; 执行抛光所述第一插塞材料（4）直到所述第一层间绝缘膜（3）露出的第一抛光; 在第一次抛光之后，在第一插头材料（4）和第一层间绝缘膜（3）上沉积成为当前操舵元件（10）的第一电极（6）的导电膜（6a） 并进行抛光导电膜（6a）的表面的第二研磨。

公开(公告)号：US07833901B2

公开(公告)日：2010-11-16

申请号：US11591704

申请日：2006-11-02

申请人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

发明人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

IPC分类号： H01L21/4763

CPC分类号： H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.

摘要翻译： 在制造其中形成具有金属布线结构的至少一个绝缘层结构从而构成多层布线布置的半导体器件的方法中，制造第一SiOCH层。 然后，处理第一SiOCH层的表面部分以将第一SiOCH层的表面部分改变为具有比（C）密度低于第一SiOCH层的碳（C）密度的第二SiOCH层，氢（H）密度 低于第一SiOCH层，氧（O）密度高于第一SiOCH层。 最后，在第二SiOCH层上形成二氧化硅（SiO 2）层。

公开(公告)号：US20100193760A1

公开(公告)日：2010-08-05

申请号：US12669174

申请日：2008-07-11

申请人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： H01L45/00 ,  H01L27/04 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

摘要翻译： 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US20100090193A1

公开(公告)日：2010-04-15

申请号：US12445380

申请日：2007-10-12

申请人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

发明人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

摘要翻译： 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29）以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US20090236747A1

公开(公告)日：2009-09-24

申请号：US12382624

申请日：2009-03-19

申请人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76853 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76861 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.

摘要翻译： 半导体器件中的多层互连结构包括形成在半导体晶片（1）上的第一绝缘层（2），形成在第一绝缘层（2）上的Cu互连层（4），形成第二绝缘层（6） 在Cu互连层（4）上形成的金属氧化物层（5）形成在Cu互连层（4）与第二绝缘层（6）之间的界面处。 通过在Cu互连层（4）上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理，形成金属氧化物层（5）。

公开(公告)号：US07388291B2

公开(公告)日：2008-06-17

申请号：US11063565

申请日：2005-02-24

申请人： Tetsuya Kurokawa ,  Koji Arita

发明人： Tetsuya Kurokawa ,  Koji Arita

IPC分类号： H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having interconnects is reduced in leakage current between the interconnects and improved in the TDDB characteristic. It includes an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, including a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.

摘要翻译： 具有互连的半导体器件减少了互连之间的漏电流并且改善了TDDB特性。 它包括绝缘夹层108和填充在绝缘中间层中形成的凹槽中的互连160，其中包括厚度小于凹槽深度的铜主要由铜组成的铜层124和低膨胀金属层140， 是形成在铜层上的具有小于铜层的热膨胀系数的金属层。

公开(公告)号：US20080029402A1

公开(公告)日：2008-02-07

申请号：US11882177

申请日：2007-07-31

申请人： Tetsuya Kurokawa ,  Koji Arita ,  Kaori Noda

发明人： Tetsuya Kurokawa ,  Koji Arita ,  Kaori Noda

IPC分类号： C25D7/12 ,  C25D17/00

CPC分类号： C25D21/22 ,  C25D7/123 ,  C25D17/001 ,  C25D17/002 ,  H01L21/2885

摘要： An electrochemical processing apparatus is provided, in which a substrate and an anode placed in a chamber are partitioned into a cathode region including the substrate and an anode region including the anode by placing a multi-layered structure of a filtration film and a cation exchange film so that the filtration film is positioned on the substrate side. A plating solution containing additives is introduced into the cathode region, whereby a substrate is plated.

摘要翻译： 提供了一种电化学处理装置，其中通过放置过滤膜和阳离子交换膜的多层结构，将放置在室中的基板和阳极分隔成包括基板的阴极区域和包括阳极的阳极区域 使得过滤膜位于基板侧。 将含有添加剂的镀液引入阴极区域，由此镀敷基板。

公开(公告)号：US06380580B1

公开(公告)日：2002-04-30

申请号：US09925705

申请日：2001-08-10

申请人： Koji Arita

发明人： Koji Arita

IPC分类号： H01G4008

CPC分类号： H01L28/75 ,  H01L28/55

摘要： A method of making a top electrode for a thin film capacitor with a multi-layer structure that includes a high dielectric oxide layer, a first conductive layer on the high dielectric oxide layer and having a high formability to a reactive ion etching, and a second conductive layer on the first conductive layer, the second conductive layer having a high formability to the reactive ion etching. The first conductive layer is deposited with a lower deposition rate than the second conductive layer wherein an interface between the first conductive layer and the high dielectric oxide layer is such that a density of a leak current across the interface is suppressed at not higher than 1×10−8 A/cm2 upon applying a voltage of 2V across the dielectric oxide layer after the multi-layer structure has been subjected to a heat treatment at 350° C.

摘要翻译： 一种制造具有多层结构的薄膜电容器的顶部电极的方法，所述多层结构包括高电介质氧化物层，高电介质氧化物层上的第一导电层和对反应离子蚀刻具有高可成形性的方法，以及第二 导电层，第二导电层对反应离子蚀刻具有高成形性。 以比第二导电层更低的沉积速率沉积第一导电层，其中第一导电层和高电介质氧化物层之间的界面使得跨越界面的漏电流的密度被抑制在不高于1×10 -3 在多层结构在350℃进行热处理后，在电介质氧化物层上施加2V的电压时为8A / cm2。

公开(公告)号：US06281534B1

公开(公告)日：2001-08-28

申请号：US09170417

申请日：1998-10-13

申请人： Koji Arita ,  Shinichiro Hayashi ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

发明人： Koji Arita ,  Shinichiro Hayashi ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

IPC分类号： H01L2976

CPC分类号： H01L21/31691 ,  H01L27/10852

摘要： A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.

摘要翻译： 用于在集成电路中形成铁电体金属氧化物薄膜的液体前体包含超过化学计量平衡量的金属氧化物。 当前体包含用于形成铌酸铋钽酸铋的锶，铋，钽和铌时，前体含有过量的钽和铌中的至少一种。 含有由含有过量的钽和铌的前体制成的层状超晶格材料的薄膜的电容器在75℃下在1010个负极化开关脉冲之后和在125℃的109个负极化开关脉冲之后显示出良好的极化率和低百分比印记。