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503 条记录 (耗时 0.05 秒)

    Methods of etching features into substrates
    22.
    发明申请
    Methods of etching features into substrates 有权
    将特征蚀刻到基底中的方法

    公开(公告)号：US20070020936A1

    公开(公告)日：2007-01-25

    申请号：US11185229

    申请日：2005-07-19

    申请人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Aaron Wilson ,  Tony Schrock

    发明人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Aaron Wilson ,  Tony Schrock

    IPC分类号： C23F1/00 ,  H01L21/302

    CPC分类号： H01L21/3081 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/906 ,  Y10S438/945

    摘要： The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.

    摘要翻译： 本发明包括将特征蚀刻到基底中的方法。 在待蚀刻的基板的材料上形成多个硬掩模层。 在这样的层中形成特征图案。 使用其中具有特征图案的硬掩模层作为掩模，将特征部分地蚀刻到基底材料中。 在部分蚀刻之后，相对于衬底材料选择性蚀刻至少一个硬掩模层，并保留硬掩模层。 在蚀刻至少一个硬掩模层之后，使用至少最内侧的硬掩模层作为掩模将特征进一步蚀刻到基底材料中。 在进一步蚀刻之后，从衬底去除最内层的硬掩模层和剩余的硬掩模层，并且将特征的至少一部分结合到集成电路中。

    Method to reduce charge buildup during high aspect ratio contact etch
    23.
    发明申请
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号：US20070049018A1

    公开(公告)日：2007-03-01

    申请号：US11213283

    申请日：2005-08-26

    申请人： Gurtej Sandhu ,  Max Hineman ,  Daniel Steckert ,  Jingyi Bai ,  Shane Trapp ,  Tony Schrock

    发明人： Gurtej Sandhu ,  Max Hineman ,  Daniel Steckert ,  Jingyi Bai ,  Shane Trapp ,  Tony Schrock

    IPC分类号： H01L21/44 ,  H01L21/302

    CPC分类号： H01L21/76802 ,  H01L21/31116 ,  Y10S438/906

    摘要： A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译： 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Antireflective coating for use during the manufacture of a semiconductor device
    27.
    发明申请
    Antireflective coating for use during the manufacture of a semiconductor device 审中-公开
    在制造半导体器件期间使用的抗反射涂层

    公开(公告)号：US20060220184A1

    公开(公告)日：2006-10-05

    申请号：US11214376

    申请日：2005-08-29

    申请人： Zhiping Yin ,  Gurtej Sandhu

    发明人： Zhiping Yin ,  Gurtej Sandhu

    IPC分类号： H01L23/58

    CPC分类号： H01L27/10888 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/90

    摘要： An antireflective layer formed from boron-doped amorphous carbon may be removed using a process which is less likely to over etch a dielectric layer than conventional technology. This layer may be removed by exposing the layer to an oxygen plasma (i.e. an “ashing” process), preferably concurrently with the ashing and removal of an overlying photoresist layer. An inventive process which uses the inventive antireflective layer is also described.

    摘要翻译： 可以使用与常规技术相比不太可能过蚀刻电介质层的方法来去除由硼掺杂的非晶碳形成的抗反射层。 可以通过将层暴露于氧等离子体（即，“灰化”工艺），优选地与上覆的光致抗蚀剂层的灰化和去除同时地去除该层。 还描述了使用本发明的抗反射层的本发明的方法。

    MASKING METHODS
    30.
    发明申请
    MASKING METHODS 有权
    掩蔽方法

    公开(公告)号：US20050042879A1

    公开(公告)日：2005-02-24

    申请号：US10652174

    申请日：2003-08-22

    申请人： Zhiping Yin ,  Gurtej Sandhu

    发明人： Zhiping Yin ,  Gurtej Sandhu

    IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/336 ,  H01L21/30 ,  H01L21/3205 ,  H01L21/46 ,  H01L21/4763

    CPC分类号： H01L21/3086 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/6653 ,  Y10S438/945 ,  Y10S438/952

    摘要： The invention includes masking methods. In one implementation, a masking material comprising boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material comprises at least about 0.5 atomic percent boron. The masking material is substantially anisotropically etched effective to form an anisotropically etched sidewall spacer comprising the boron doped amorphous carbon on a sidewall of the feature. The substrate is then processed proximate the spacer while using the boron doped amorphous carbon comprising spacer as a mask. After processing the substrate proximate the spacer, the boron doped amorphous carbon comprising spacer is etched from the substrate. Other implementations and aspects are contemplated.

    摘要翻译： 本发明包括掩蔽方法。 在一个实施方案中，在形成在半导体衬底上的特征上形成包含硼掺杂的非晶碳的掩模材料。 掩模材料包含至少约0.5原子％的硼。 掩模材料基本上是各向异性蚀刻有效地形成各向异性蚀刻的侧壁间隔物，其包含该特征侧壁上的硼掺杂无定形碳。 然后使用包含间隔物的硼掺杂的无定形碳作为掩模，然后在衬垫附近处理衬底。 在靠近间隔物处理衬底之后，从衬底上蚀刻包含衬底的硼掺杂非晶碳。 考虑其他实现和方面。