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    Dual-mode memory devices and methods for operating same
    23.
    发明授权
    Dual-mode memory devices and methods for operating same 有权
    双模式存储器件和操作方法

    公开(公告)号：US09461175B2

    公开(公告)日：2016-10-04

    申请号：US14209962

    申请日：2014-03-13

    Applicant: Macronix International Co., Ltd.

    Inventor： Hang-Ting Lue ,  Wei-Chen Chen

    IPC: G11C16/04 ,  H01L29/786 ,  H01L29/423 ,  H01L29/739 ,  H01L27/092 ,  H01L29/66 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

    CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

    Abstract: A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase.

    Abstract translation: 存储器结构包括具有多栅极沟道区的半导体条，与沟道区的第一侧相邻的p型端子区和与沟道区的第二侧相邻的n型端子区。 多个字线布置成在沟道区域的交叉点处穿过半导体条。 位线耦合到半导体条的第一端，并且参考线耦合到半导体条的第二端。 电荷存储结构设置在多个字线中的字线和半导体条的沟道区之间，由此存储单元沿着位线和参考线之间的半导体条串联设置。 可以使用偏移未选择的字线来选择单个所选单元格中的n沟道或p沟道模式进行读取，编程或擦除。

    3D SEMICONDUCTOR DEVICE AND ARRAY LAYOUT THEREOF
    27.
    发明公开
    3D SEMICONDUCTOR DEVICE AND ARRAY LAYOUT THEREOF 审中-公开

    公开(公告)号：US20230269944A1

    公开(公告)日：2023-08-24

    申请号：US18308594

    申请日：2023-04-27

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh ,  Guan-Ru Lee

    IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L21/0217

    Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

    THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES
    28.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 有权

    公开(公告)号：US20230070119A1

    公开(公告)日：2023-03-09

    申请号：US17695943

    申请日：2022-03-16

    Applicant: Macronix International Co., Ltd.

    Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh

    IPC: H01L27/11

    Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME AND METHOD FOR OPERATING THE SAME
    29.
    发明申请
    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME AND METHOD FOR OPERATING THE SAME 有权

    公开(公告)号：US20220293628A1

    公开(公告)日：2022-09-15

    申请号：US17249701

    申请日：2021-03-10

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wei-Chen Chen ,  Hang-Ting Lue

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

    Abstract: A memory device includes a stack and a plurality of memory strings respectively penetrating the stack along the first direction and including adjacent ones of the first memory string and the second memory string. The first memory string and the second memory string include conductive pillars (including first to third conductive pillars), channel structures, and memory structures. The first memory string and the second memory string share the second conductive pillar. The channel structures include first to fourth channel layers respectively extending along the first direction. The first channel layer and the second channel layer correspond to the first memory string and are separated from each other. The third channel layer and the fourth channel layer correspond to the second memory string and are separated from each other. The memory structures are disposed between the stack and the channel structures.

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