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    CORRECTIVE READS IMPLEMENTING INCREMENTAL READS WITH RESPECT TO ADJACENT WORDLINES
    21.
    发明公开
    CORRECTIVE READS IMPLEMENTING INCREMENTAL READS WITH RESPECT TO ADJACENT WORDLINES 审中-公开

    公开(公告)号：US20230305717A1

    公开(公告)日：2023-09-28

    申请号：US18125279

    申请日：2023-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Dheeraj Srinivasan ,  Luanming Deng

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A system includes a memory device including a memory array and control logic operatively coupled with the memory array. The memory array includes a target cell connected to a target wordline, a first cell connected to a first adjacent wordline adjacent to the target wordline, and a second cell connected to a second adjacent wordline adjacent to the target wordline. The control logic performs operations including causing a read to be performed with respect to the first cell to obtain an adjacent wordline read result, storing the adjacent wordline read result using a first set of page buffers, causing an incremental read to be performed with respect to the second cell and a first bin to obtain a first incremental read result, and storing the first incremental read result using a second set of page buffers.

    Bitline driver isolation from page buffer circuitry in memory device
    22.
    发明授权
    Bitline driver isolation from page buffer circuitry in memory device 有权

    公开(公告)号：US11688466B2

    公开(公告)日：2023-06-27

    申请号：US17678960

    申请日：2022-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

    Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The circuit coupled to the dynamic memory element can perform a first operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

    INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE
    23.
    发明申请
    INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE 有权

    公开(公告)号：US20230059543A1

    公开(公告)日：2023-02-23

    申请号：US17887940

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

    IPC: G06F3/06

    Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

    Bitline driver isolation from page buffer circuitry in memory device
    25.
    发明授权
    Bitline driver isolation from page buffer circuitry in memory device 有权

    公开(公告)号：US11276470B2

    公开(公告)日：2022-03-15

    申请号：US16947091

    申请日：2020-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

    Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The one or more bitline driver circuits can perform a first pre-charging operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

    CONTINUOUS MEMORY PROGRAMMING OPERATIONS
    30.
    发明申请
    CONTINUOUS MEMORY PROGRAMMING OPERATIONS 有权

    公开(公告)号：US20240428872A1

    公开(公告)日：2024-12-26

    申请号：US18800552

    申请日：2024-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

    IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

    Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

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