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公开(公告)号：US20230059543A1
公开(公告)日：2023-02-23
申请号：US17887940
申请日：2022-08-15
发明人： Andrea Giovanni Xotta , Dheeraj Srinivasan , Ali Mohammadzadeh , Karl D. Schuh , Guido Luciano Rizzo , Jung Sheng Hoei , Michele Piccardi , Tommaso Vali , Umberto Siciliani , Rohitkumar Makhija , June Lee , Aaron S. Yip , Daniel J. Hubbard
IPC分类号： G06F3/06
摘要： A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.
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公开(公告)号：US11562791B1
公开(公告)日：2023-01-24
申请号：US17396825
申请日：2021-08-09
发明人： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
摘要： Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
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公开(公告)号：US11276470B2
公开(公告)日：2022-03-15
申请号：US16947091
申请日：2020-07-17
摘要： A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The one or more bitline driver circuits can perform a first pre-charging operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.
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公开(公告)号：US20210181955A1
公开(公告)日：2021-06-17
申请号：US17187066
申请日：2021-02-26
IPC分类号： G06F3/06 , G06F12/0811
摘要： The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
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公开(公告)号：US10977186B2
公开(公告)日：2021-04-13
申请号：US15819941
申请日：2017-11-21
IPC分类号： G06F12/02 , G06F3/06 , G06F12/1009 , G11C11/56 , G06F11/07
摘要： An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.
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公开(公告)号：US10372353B2
公开(公告)日：2019-08-06
申请号：US15609569
申请日：2017-05-31
IPC分类号： G06F12/00 , G06F13/00 , G06F3/06 , G06F12/0811
摘要： The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
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公开(公告)号：US20180349029A1
公开(公告)日：2018-12-06
申请号：US15609569
申请日：2017-05-31
IPC分类号： G06F3/06 , G06F12/0811
CPC分类号： G06F3/0619 , G06F3/0616 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F12/0811 , G06F2212/283 , G06F2212/601
摘要： The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
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公开(公告)号：US12079134B2
公开(公告)日：2024-09-03
申请号：US18178105
申请日：2023-03-03
IPC分类号： G06F12/08 , G06F12/0891
CPC分类号： G06F12/0891
摘要： Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.
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公开(公告)号：US20240231675A1
公开(公告)日：2024-07-11
申请号：US18611094
申请日：2024-03-20
发明人： Eric N. Lee , Dheeraj Srinivasan
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0673
摘要： A memory system includes a ready busy pin coupled with a plurality of dice and a processing device coupled with the ready busy pin. The processing device is to perform controller operations including waiting to perform any status checks until after assertion of a pulse on a status indicator signal received from the ready busy pin; detecting the pulse being asserted is an extended pulse comprising at least a partial overlap of a first pulse asserted by a first die and a second pulse asserted by a second die of the plurality of dice; initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of the first pulse; and initiating a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.
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30.发明公开公开(公告)号：US20230367680A1
公开(公告)日：2023-11-16
申请号：US18143937
申请日：2023-05-05
发明人： Lu Tong , Ashish Ghai , Chai Chuan Yao , Ekamdeep Singh , Lakshmi Kalpana Vakati , Sheng Huang Lee , Matthew Ivan Warren , Dheeraj Srinivasan , Jeffrey Ming-Hung Tsai
CPC分类号： G06F11/2023 , G06F3/0617 , G06F3/064 , G06F3/0673 , G06F2201/805
摘要： Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.
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