公开(公告)号：US11665893B2

公开(公告)日：2023-05-30

申请号：US15255967

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun Jeff Hu ,  Haitao Liu

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

公开(公告)号：US11658246B2

公开(公告)日：2023-05-23

申请号：US16596370

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Ramanathan Gandhi ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Scott E. Sills

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L29/78

CPC classification number: H01L29/78642 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/7869 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device comprises a vertical transistor. The vertical transistor comprises a pillar structure, at least one gate electrode, and a dielectric material. The pillar structure comprises a source region, a drain region, and a channel region. The source region and the drain region each individually comprise at least one electrically conductive material configured to inhibit hydrogen permeation therethrough. The channel region comprises a semiconductive material vertically between the source region and the drain region. The at least one gate electrode laterally neighbors the channel region of the semiconductive structure. The dielectric material is laterally between the semiconductive structure and the at least one gate electrode. Additional devices, and related electronic systems and methods are also disclosed.

公开(公告)号：US11658242B2

公开(公告)日：2023-05-23

申请号：US17524653

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L27/108 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L29/7827 ,  H01L27/10808 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/456

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.

公开(公告)号：US11653489B2

公开(公告)日：2023-05-16

申请号：US17003054

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/108 ,  H01L29/24 ,  G11C5/06

CPC classification number: H01L27/10802 ,  G11C5/063 ,  H01L27/10844 ,  H01L29/24

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

公开(公告)号：US20230143406A1

公开(公告)日：2023-05-11

申请号：US18083412

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US11616073B1

公开(公告)日：2023-03-28

申请号：US17514979

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Eric S. Carman ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Haitao Liu

IPC: H01L27/11575 ,  H01L29/423 ,  H01L29/10

Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

公开(公告)号：US11563010B2

公开(公告)日：2023-01-24

申请号：US16666709

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Haitao Liu

IPC: H01L27/108 ,  H01L27/06 ,  H01L21/8254 ,  H01L29/10

Abstract: Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11527620B2

公开(公告)日：2022-12-13

申请号：US17317668

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20220392533A1

公开(公告)日：2022-12-08

申请号：US17888041

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US11495600B2

公开(公告)日：2022-11-08

申请号：US17093869

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Litao Yang

IPC: H01L27/108 ,  G11C11/408

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having vertically oriented access devices having a first source/drain region and a second source drain region vertically separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the first source/drain region and horizontally oriented digit lines coupled to the second source/drain regions.