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    Arrays Of Nonvolatile Memory Cells
    21.
    发明申请
    Arrays Of Nonvolatile Memory Cells 有权
    非易失性存储单元阵列

    公开(公告)号：US20150078056A1

    公开(公告)日：2015-03-19

    申请号：US14551206

    申请日：2014-11-24

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C5/02 ,  G11C13/00

    CPC classification number: G11C5/02 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F2 within an individual of the tiers. Also disclosed is an array of nonvolatile memory cells comprising a plurality of unit cells which individually comprise three elevational regions of programmable material, the three elevational regions comprising the programmable material of at least three different memory cells of the unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells. Other embodiments and aspects are disclosed.

    Abstract translation: 公开了一种非易失性存储单元的阵列，每个单元具有五个存储单元。 还公开了一种非易失性存储器单元的垂直堆叠层的阵列，其包括在层的个体内占据4F2的连续水平面积的五个存储单元。 还公开了一种非易失性存储单元的阵列，其包括单独包含可编程材料的三个高程区域的多个单位单元，所述三个高程区域包括该单位单元的至少三个不同存储单元的可编程材料。 还公开了一种垂直堆叠层的非易失性存储单元的阵列，其包括具有多个垂直取向的存储单元和多个水平定向存储单元的组合的连续体积。 公开了其它实施例和方面。

    STT-MRAM cell structures
    24.
    发明授权
    STT-MRAM cell structures 有权
    STT-MRAM细胞结构

    公开(公告)号：US08945950B2

    公开(公告)日：2015-02-03

    申请号：US14037064

    申请日：2013-09-25

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H01L21/00 ,  H01L29/66 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/66007 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

    Abstract translation: 提供包括非磁性桥的磁性单元结构以及制造该结构的方法。 磁性电池结构包括自由层，钉扎层和电连接自由层和钉扎层的非磁性桥。 非磁性桥的形状和/或构造使编程电流通过磁性单元结构，使得结构自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

    RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION
    25.
    发明申请
    RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION 有权
    具有确定的光纤形成的电阻记忆

    公开(公告)号：US20150021541A1

    公开(公告)日：2015-01-22

    申请号：US14478408

    申请日：2014-09-05

    Applicant: Micron Technology, Inc.

    Inventor： Eugene P. Marsh ,  Jun Liu

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

    Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.

    Abstract translation: 本文描述了具有限制的灯丝形成的电阻记忆。 一个或多个方法实施例包括在硅材料上形成具有硅材料和氧化物材料的堆叠中的开口，以及在邻近硅材料的开口中形成氧化物材料，其中形成在开口中的氧化物材料限制在 电阻性存储单元到形成在开口中的氧化物材料包围的区域。

    Memory cell constructions, and methods for fabricating memory cell constructions
    26.
    发明授权
    Memory cell constructions, and methods for fabricating memory cell constructions 有权

    公开(公告)号：US08921823B2

    公开(公告)日：2014-12-30

    申请号：US14243710

    申请日：2014-04-02

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Jian Li

    IPC: H01L45/00 ,  H01L21/06

    CPC classification number: H01L45/1608 ,  H01L21/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675

    Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

    Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells
    29.
    发明申请
    Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells 有权
    记忆单元阵列和形成记忆单元阵列的方法

    公开(公告)号：US20140217350A1

    公开(公告)日：2014-08-07

    申请号：US13761570

    申请日：2013-02-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    Abstract translation: 存储单元阵列包括具有导电掺杂半导体材料的掩埋访问线。 支柱向外延伸并沿着掩埋的进入管线间隔开。 支柱分别包括一个记忆单元。 外部接入线在柱子和埋入式接入线路的正上方。 外部接入线路比埋入式接入线路的导电性高。 多个导电通孔沿着并且电耦合埋入和外部接入线路中的各个对间隔开。 多个支柱在沿对之间的通孔的紧邻之间。 导电金属材料直接抵靠埋入式接入线路的顶部，并沿独立的埋入式接入线路在支柱之间延伸。 公开了包括方法的其它实施例。

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