公开(公告)号：US20170104156A1

公开(公告)日：2017-04-13

申请号：US15383105

申请日：2016-12-19

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

CPC classification number: H01L45/1273 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

公开(公告)号：US20170025517A1

公开(公告)日：2017-01-26

申请号：US15284017

申请日：2016-10-03

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC: H01L29/66 ,  H01L27/102 ,  H01L29/74 ,  H01L29/423

CPC classification number: H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract translation: 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

公开(公告)号：US20150303239A1

公开(公告)日：2015-10-22

申请号：US14790535

申请日：2015-07-02

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L27/24 ,  H01L21/02 ,  H01L29/66 ,  H01L45/00

CPC classification number: H01L27/2409 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/33 ,  G11C2213/72 ,  H01L21/02532 ,  H01L21/31116 ,  H01L27/1021 ,  H01L27/2463 ,  H01L29/66136 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608

Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

Abstract translation: 一些实施例包括具有耦合到存储器元件的二极管的存储器件的装置和方法。 每个二极管可以形成在存储器件的凹部中。 凹部可以具有多边形侧壁。 二极管可以包括形成在凹槽内的第一导电类型（例如，n型）和第二导电类型（例如，p型）的第一材料。

公开(公告)号：US20140051214A1

公开(公告)日：2014-02-20

申请号：US13761587

申请日：2013-02-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract translation: 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US20130153849A1

公开(公告)日：2013-06-20

申请号：US13758644

申请日：2013-02-04

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

CPC classification number: H01L45/143 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.

公开(公告)号：US20210193916A1

公开(公告)日：2021-06-24

申请号：US17135102

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element, Other embodiments are described.

公开(公告)号：US20210043525A1

公开(公告)日：2021-02-11

申请号：US16535882

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James E. Davis

IPC: H01L21/66 ,  H01L27/11556 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US10573812B2

公开(公告)日：2020-02-25

申请号：US16127984

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L27/10

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

公开(公告)号：US20190027684A1

公开(公告)日：2019-01-24

申请号：US16127984

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L27/10

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

公开(公告)号：US09356096B2

公开(公告)日：2016-05-31

申请号：US14803662

申请日：2015-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Song Guo ,  Yushi Hu ,  Roy Meade ,  Sanh D. Tang ,  Michael P. Violette ,  David H. Wells

IPC: H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/32

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/04 ,  H01L29/32

Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.