公开(公告)号：US11670372B2

公开(公告)日：2023-06-06

申请号：US17452505

申请日：2021-10-27

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.

公开(公告)号：US20230031362A1

公开(公告)日：2023-02-02

申请号：US17387669

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/28

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

公开(公告)号：US20220189565A1

公开(公告)日：2022-06-16

申请号：US17689862

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

公开(公告)号：US20250087275A1

公开(公告)日：2025-03-13

申请号：US18768970

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Shyam Sunder Raghunathan ,  Yingda Dong ,  Akira Goda

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/28

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.

公开(公告)号：US12217801B2

公开(公告)日：2025-02-04

申请号：US18076537

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US11956954B2

公开(公告)日：2024-04-09

申请号：US17092916

申请日：2020-11-09

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Yan Song ,  Albert Fayrushin ,  Naiming Liu ,  Yingda Dong ,  George Matamis

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

公开(公告)号：US20240096408A1

公开(公告)日：2024-03-21

申请号：US18371308

申请日：2023-09-21

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Yingda Dong

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/2254

Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.

公开(公告)号：US20240028253A1

公开(公告)日：2024-01-25

申请号：US18224538

申请日：2023-07-20

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Ching-Huang Lu ,  Aman Gupta ,  Shuji Tanaka ,  Masashi Yoshida ,  Shinji Sato ,  Yingda Dong

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

公开(公告)号：US11749359B2

公开(公告)日：2023-09-05

申请号：US17702525

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3413

Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.

公开(公告)号：US20230195328A1

公开(公告)日：2023-06-22

申请号：US18082803

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Yingda Dong ,  Sampath K. Ratnam

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0652

Abstract: Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.