公开(公告)号：US09142454B1

公开(公告)日：2015-09-22

申请号：US14215149

申请日：2014-03-17

Applicant: Macronix International Co., Ltd.

Inventor： Guan-Ru Lee ,  Yu-Wei Jiang

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76829 ,  H01L21/76816 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a first conductive structure, a second conductive structure, a dielectric structure, a dielectric layer, a first conductive plug, and a second conductive plug. The first conductive plug passes through only an upper dielectric portion of the dielectric structure, the dielectric layer and a lower dielectric portion of the dielectric structure to physically and electrically contact with the first conductive structure. The second conductive plug passes through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact with the second conductive structure.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括衬底，第一导电结构，第二导电结构，电介质结构，电介质层，第一导电插塞和第二导电插塞。 第一导电插塞仅穿过电介质结构的上电介质部分，电介质层和电介质结构的下电介质部分，以与第一导电结构物理和电接触。 第二导电插塞穿过上电介质部分，电介质层和下电介质部分以物理地和电接触第二导电结构。

公开(公告)号：US10312256B1

公开(公告)日：2019-06-04

申请号：US15814582

申请日：2017-11-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: H01L21/02 ,  H01L27/11582 ,  H01L29/04 ,  H01L21/28 ,  H01L21/768 ,  H01L21/311 ,  H01L29/16 ,  H01L29/10 ,  H01L23/535 ,  H01L29/51

Abstract: A three-dimensional (3D) stacked semiconductor structure is provided. A substrate having an array area and a peripheral area is provided, and several patterned multi-layered stacks above the substrate are formed in the array area. The patterned multi-layered stacks are spaced apart from each other, and channel holes are formed between the patterned multi-layered stacks disposed adjacently. A charge trapping layer is formed on the patterned multi-layered stacks and deposited in the channel holes as liners. A polysilicon channel layer is deposited along the charge trapping layer, and conductive pads are formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks. The polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), wherein the second thickness (t2) is larger than the first thickness (t1).

公开(公告)号：US09583503B1

公开(公告)日：2017-02-28

申请号：US14966173

申请日：2015-12-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: H01L27/115 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/06 ,  H01L21/822

CPC classification number: H01L27/11578 ,  H01L21/32055 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device is provided, comprising: a plurality of ground selection line (GSL) sections separately formed on a substrate, the GSL sections being electrically insulated from each other and extended in parallel to each other, and the GSL sections extending along a first direction; a plurality of stacked structures vertically formed on the GSL sections on the substrate, and each stacked structure comprising alternated semiconductor layers and insulating layers; string selection lines (SSLs) separately formed on the stacked structures, and the string selection lines extending along the first direction; and bit lines disposed above the SSLs and extending along a second direction, the bit lines arranged parallel to each other and in perpendicular to the SSLs and GSL sections, wherein a plurality of memory cells of memory layers respectively defined by the stacked structures, the SSLs, the GSL sections and the bit lines correspondingly.

Abstract translation: 提供一种三维半导体器件，包括：分别形成在衬底上的多个接地选择线（GSL）部分，所述GSL部分彼此电绝缘并且彼此平行延伸，并且GSL部分沿着 第一个方向 垂直形成在基板上的GSL部分上的多个堆叠结构，并且每个层叠结构包括交替的半导体层和绝缘层; 所述串选择线（SSL）分别形成在所述堆叠结构上，所述串选择线沿着所述第一方向延伸; 以及设置在所述SSL之上并且沿着第二方向延伸的位线，所述位线彼此平行并且垂直于所述SSL和GSL部分布置，其中分别由所述堆叠结构限定的多个存储器层的存储单元，所述SSL ，GSL部分和位线相应。

公开(公告)号：US09425202B2

公开(公告)日：2016-08-23

申请号：US14670105

申请日：2015-03-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C5/06 ,  H01L27/115 ,  G11C5/02 ,  G11C7/14 ,  G11C11/56

CPC classification number: H01L27/115 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines.

公开(公告)号：US09293348B2

公开(公告)日：2016-03-22

申请号：US14143040

申请日：2013-12-30

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  Yen-Hao Shih

IPC: H01L23/528 ,  H01L27/105 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/768 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/32133 ,  H01L21/32055 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括基板，堆叠结构，电介质层，导电结构，电介质结构和导电插塞。 堆叠结构包括交替布置的介电膜和导电膜。 介电层位于导电结构和层叠结构的侧壁之间。 电介质结构在堆叠结构上并且限定通孔。 导电插塞填充通孔并物理地接触由通孔暴露并与电介质层相邻的导电膜之一。

公开(公告)号：US20150262871A1

公开(公告)日：2015-09-17

申请号：US14215149

申请日：2014-03-17

Applicant: Macronix International Co., Ltd.

Inventor： Guan-Ru Lee ,  Yu-Wei Jiang

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76829 ,  H01L21/76816 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a first conductive structure, a second conductive structure, a dielectric structure, a dielectric layer, a first conductive plug, and a second conductive plug. The first conductive plug passes through only an upper dielectric portion of the dielectric structure, the dielectric layer and a lower dielectric portion of the dielectric structure to physically and electrically contact with the first conductive structure. The second conductive plug passes through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact with the second conductive structure.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括衬底，第一导电结构，第二导电结构，电介质结构，电介质层，第一导电插塞和第二导电插塞。 第一导电插塞仅穿过电介质结构的上电介质部分，电介质层和电介质结构的下电介质部分，以与第一导电结构物理和电接触。 第二导电插塞穿过上电介质部分，电介质层和下电介质部分以物理地和电接触第二导电结构。

公开(公告)号：US09023701B1

公开(公告)日：2015-05-05

申请号：US14145162

申请日：2013-12-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Ru Lee

IPC: H01L21/336 ,  H01L29/788 ,  H01L27/115 ,  H01L21/265 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A method of forming a three-dimensional memory is provided. A stacked structure is patterned to form a comb structure including a bit line pad extending along a first direction and comb-teeth portions extending along a second direction. A charge storage layer is formed on top and sidewall of the comb structure. Bit lines and auxiliary gates are formed on the charge storage layer and extend along the first direction. Each bit line covers top and sidewall of partial comb-teeth portions. Auxiliary gates cover top and sidewall of edge regions of the bit line pad. The charge storage layer on top of the bit line pad is removed. The stacked structure of the bit line pad is patterned to form a stepped structure. An ion implantation is performed to the stepped structure, to form a doped region in the semiconductor layer below each step surface of the stepped structure.

Abstract translation: 提供了形成三维存储器的方法。 图案化堆叠结构以形成包括沿着第一方向延伸的位线焊盘和沿着第二方向延伸的梳齿部分的梳状结构。 电容存储层形成在梳结构的顶部和侧壁上。 位线和辅助栅极形成在电荷存储层上并沿着第一方向延伸。 每个位线覆盖部分梳齿部分的顶部和侧壁。 辅助栅极覆盖位线焊盘边缘区域的顶部和侧壁。 去除位线焊盘顶部的电荷存储层。 图案化位线焊盘的堆叠结构以形成阶梯状结构。 对台阶结构进行离子注入，以在阶梯状结构的每个台阶表面的半导体层内形成掺杂区域。

公开(公告)号：US20150117101A1

公开(公告)日：2015-04-30

申请号：US14062487

申请日：2013-10-24

Applicant: Macronix International Co., Ltd.

Inventor： Guan-Ru Lee

IPC: G11C16/04 ,  H01L27/115

CPC classification number: H01L27/115 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines.

公开(公告)号：US20150091076A1

公开(公告)日：2015-04-02

申请号：US14044593

申请日：2013-10-02

Applicant: Macronix International Co. Ltd.

Inventor： Guan-Ru Lee

IPC: H01L21/8234 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/792 ,  G11C16/0408 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: A method for manufacturing a memory device includes providing a substrate having a plurality of active layers, forming a plurality of holes through the plurality of active layers including a first row of holes and a second row of holes, and filling the plurality of holes with an isolation material. The method includes etching the plurality of active layers to form first and second sets of interdigitated stacks of active strips, where the first set includes strips extending from pads in a first stack of pads and terminating at isolation strips remaining from corresponding filled holes in the first row, and the second set includes strips extending from pads in a second stack of pads and terminating at isolation strips remaining from corresponding filled holes in the second row.

Abstract translation: 一种用于制造存储器件的方法，包括提供具有多个有源层的衬底，通过包括第一排孔和第二排孔的多个有源层形成多个孔，并且用一个 隔离材料。 该方法包括蚀刻多个有源层以形成第一组和第二组互相交叠的有源带堆叠，其中第一组包括从第一堆叠焊盘中的焊盘延伸的条带，并且终止于在第一堆 并且第二组包括从第二堆叠焊盘中的焊盘延伸的条带，并且在从第二行中的相应填充孔残留的隔离条上终止。

公开(公告)号：US20140264621A1

公开(公告)日：2014-09-18

申请号：US13798275

申请日：2013-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee ,  Erh-Kun Lai

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The method comprises following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region.

Abstract translation: 提供了一种半导体结构及其制造方法。 该方法包括以下步骤。 第一栅极结构形成在第一区域中的衬底上。 形成覆盖第一栅极结构的保护层。 第二栅极结构形成在由保护层露出并邻近第一区域的第二区域中的衬底上。