公开(公告)号：US07531407B2

公开(公告)日：2009-05-12

申请号：US11488242

申请日：2006-07-18

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/8234

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。 例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。 在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。 通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。 半导体衬底可以是SOI（绝缘体上硅）结构。

公开(公告)号：US20080020488A1

公开(公告)日：2008-01-24

申请号：US11488242

申请日：2006-07-18

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。 例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。 在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。 通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。 半导体衬底可以是SOI（绝缘体上硅）结构。

公开(公告)号：US20070007665A1

公开(公告)日：2007-01-11

申请号：US11160669

申请日：2005-07-05

申请人： Lawrence Clevenger ,  Mukta Farooq ,  Louis Hsu ,  William Landers ,  Donna Zupanski-Nielsen ,  Carl Radens ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Mukta Farooq ,  Louis Hsu ,  William Landers ,  Donna Zupanski-Nielsen ,  Carl Radens ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/49109 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

公开(公告)号：US20060249846A1

公开(公告)日：2006-11-09

申请号：US10908360

申请日：2005-05-09

申请人： Chih-Chao Yang ,  Lawrence Clevenger ,  James Demarest ,  Louis Hsu ,  Carl Radens

发明人： Chih-Chao Yang ,  Lawrence Clevenger ,  James Demarest ,  Louis Hsu ,  Carl Radens

IPC分类号： H01L23/52

CPC分类号： H01L23/5228 ,  H01L23/5256 ,  H01L23/5329 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.

摘要翻译： 本发明提供一种电可编程金属电阻器及其制造方法，其中电迁移应力用于在结构中产生增加电阻器的电阻的空隙。 具体而言，提供一种半导体结构，其包括包括至少一个电介质层的互连结构，其中所述至少一个电介质层包括至少两个导电区域和嵌入其中的覆盖互连区域，所述至少两个导电区域与 所述覆盖互连区域由至少两个触点和至少所述互连区域通过扩散阻挡层与所述至少一个介电层分离，其中空隙存在于至少互连区域中，这增加了互连区域的电阻。

公开(公告)号：US20070278619A1

公开(公告)日：2007-12-06

申请号：US11443394

申请日：2006-05-30

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US07851321B2

公开(公告)日：2010-12-14

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/20

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US20070290345A1

公开(公告)日：2007-12-20

申请号：US11847776

申请日：2007-08-30

申请人： Lawrence Clevenger ,  Mukta Farooq ,  Louis Hsu ,  William Landers ,  Donna Zupanski-Nielsen ,  Carl Radens ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Mukta Farooq ,  Louis Hsu ,  William Landers ,  Donna Zupanski-Nielsen ,  Carl Radens ,  Chih-Chao Yang

IPC分类号： H01L23/488 ,  H01L21/34

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/49109 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

摘要翻译： 一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。 第一基板包括第一导电焊盘和第二导电焊盘。 第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。 第四导电焊盘包括与第一导电构件的高度不同的高度。 导电构件电连接和机械地连接到第四导电垫。 第一焊球将第一导电焊盘连接到第三导电焊盘。 第一焊球包括第一直径。 第二焊球将第二导电焊盘连接到第一导电构件。 第二焊球包括第二直径。 第一直径大于所述第二直径。

公开(公告)号：US20050127511A1

公开(公告)日：2005-06-16

申请号：US10735845

申请日：2003-12-16

申请人： Chih-Chao Yang ,  Louis Hsu ,  Keith Wong ,  Timothy Dalton ,  Carl Radens ,  Larry Clevenger

发明人： Chih-Chao Yang ,  Louis Hsu ,  Keith Wong ,  Timothy Dalton ,  Carl Radens ,  Larry Clevenger

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76862 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.

摘要翻译： 制造互连结构的扩散阻挡层的方法。 该方法包括：在底部电介质沟槽中提供导线; 在所述盖层上沉积牺牲衬垫; 沉积层间电介质; 在顶层间电介质中形成沟槽和通孔; 以及去除靠近通孔底表面的覆盖层和牺牲层的一部分。 盖层和牺牲层的去除部分主要沿着通孔的下侧壁沉积。 导线与盖层接触，牺牲层与盖层接触。 本发明还涉及由本发明方法产生的互连结构。

公开(公告)号：US20090312046A1

公开(公告)日：2009-12-17

申请号：US12137185

申请日：2008-06-11

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

IPC分类号： H04B7/00 ,  H04M1/00

CPC分类号： H02J50/20 ,  H02J7/025 ,  H02J17/00

摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

摘要翻译： 一种用于无线网络设备智能电源管理的系统和方法。 该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。 电池通过嵌入在无线设备内部的射频收集单元进行充电。 智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。 第一个适配器设置为数据通信，而第二个适配器用于传输电源。 此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

公开(公告)号：US08024012B2

公开(公告)日：2011-09-20

申请号：US12137185

申请日：2008-06-11

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

IPC分类号： H04B1/38 ,  H04B1/16

CPC分类号： H02J50/20 ,  H02J7/025 ,  H02J17/00

摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

摘要翻译： 一种用于无线网络设备智能电源管理的系统和方法。 该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。 电池通过嵌入在无线设备内部的射频收集单元进行充电。 智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。 第一个适配器设置为数据通信，而第二个适配器用于传输电源。 此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。