公开(公告)号：US20110278542A1

公开(公告)日：2011-11-17

申请号：US12777881

申请日：2010-05-11

申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。

公开(公告)号：US20110031473A1

公开(公告)日：2011-02-10

申请号：US12536741

申请日：2009-08-06

申请人： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

发明人： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC分类号： H01L27/11 ,  H01L29/66 ,  H01L21/8239

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  Y10S977/938

摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

公开(公告)号：US20090108352A1

公开(公告)日：2009-04-30

申请号：US11931033

申请日：2007-10-31

申请人： Amlan Majumdar ,  Renee Tong Mo ,  Zhibin Ren ,  Jeffrey Sleight

发明人： Amlan Majumdar ,  Renee Tong Mo ,  Zhibin Ren ,  Jeffrey Sleight

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78606 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

摘要： Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.

摘要翻译： 提供了具有金属栅叠层的金属氧化物半导体场效应晶体管（MOSFET）器件和用于提高其性能的技术。 一方面，提供一种金属氧化物半导体器件，其包括具有掩埋氧化物层的衬底，其中至少一部分被配置为用作器件的主要背景氧吸收器; 以及通过界面氧化物层与衬底分离的栅极叠层。 栅叠层包括在界面氧化物层上的高K层; 以及高K层上的金属栅极层。

公开(公告)号：US20070184619A1

公开(公告)日：2007-08-09

申请号：US11346662

申请日：2006-02-03

申请人： John Hergenrother ,  Zhibin Ren ,  Dinkar Singh ,  Jeffrey Sleight

发明人： John Hergenrother ,  Zhibin Ren ,  Dinkar Singh ,  Jeffrey Sleight

IPC分类号： H01L21/336

CPC分类号： H01L21/28097 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/7624 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.

摘要翻译： 用于选择性地将电荷放置到栅极堆叠中的器件和方法包括形成包括邻近晶体管沟道和栅极导体的栅极电介质的栅极堆叠，并形成用于晶体管操作的掺杂区域。 在掺杂区域和栅极叠层上沉积富含钝化元素的层，并且从所选择的晶体管去除富含钝化元件的层。 富含钝化元件的层比退火以驱动钝化元件，以增加在存在钝化元件的层的晶体管上的晶体管沟槽处或附近的电荷浓度。 去除富含钝化元素的层。

公开(公告)号：US20060231893A1

公开(公告)日：2006-10-19

申请号：US11107611

申请日：2005-04-15

申请人： Kerry Bernstein ,  Jeffrey Sleight ,  Min Yang

发明人： Kerry Bernstein ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

摘要： The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

公开(公告)号：US20060175659A1

公开(公告)日：2006-08-10

申请号：US10906178

申请日：2005-02-07

申请人： Jeffrey Sleight

发明人： Jeffrey Sleight

IPC分类号： H01L27/12

CPC分类号： H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects.

摘要翻译： 本发明提供一种半导体结构，其包括具有UTSOI区域和体积-Si区域的衬底，其中UTSOI区域和体积-Si区域具有相同的晶体取向; 将UTSOI区域与体Si区域分离的隔离区域; 以及位于UTSOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 UTSOI区域在绝缘层顶上具有SOI层，其中SOI层的厚度小于约40nm。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。

公开(公告)号：US08877593B2

公开(公告)日：2014-11-04

申请号：US13194980

申请日：2011-07-31

申请人： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

发明人： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/66

CPC分类号： H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7845

摘要： A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

摘要翻译： 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

公开(公告)号：US08686506B2

公开(公告)日：2014-04-01

申请号：US13571734

申请日：2012-08-10

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC分类号： H01L29/72

CPC分类号： H01L21/823807 ,  H01L29/7847

摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力记忆技术（SMT），栅极硅化物和源极/漏极硅化物区域引起的升高的应力的NFET栅极区域和双重应力衬里，并且其中所述高密度器件 区域包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。

公开(公告)号：US08680623B2

公开(公告)日：2014-03-25

申请号：US13433815

申请日：2012-03-29

申请人： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

发明人： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC分类号： H01L21/8244 ,  H01L21/70

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108

摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

摘要翻译： 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US08338239B2

公开(公告)日：2012-12-25

申请号：US12781896

申请日：2010-05-18

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC分类号： H01L29/72

CPC分类号： H01L21/823807 ,  H01L29/7847

摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力存储技术（SMT），栅极和源极/漏极硅化物区域以及双重应力衬底引起的升高的应力的NFET栅极区域，并且其中所述高密度器件区域 包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。