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    HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT
    2.
    发明申请
    HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT 失效
    混合晶体定向CMOS结构适用于良好的偏置和功率和性能增强

    公开(公告)号：US20080009114A1

    公开(公告)日：2008-01-10

    申请号：US11859889

    申请日：2007-09-24

    申请人： Kerry Bernstein ,  Jeffrey Sleight ,  Min Yang

    发明人： Kerry Bernstein ,  Jeffrey Sleight ,  Min Yang

    IPC分类号： H01L21/8238 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

    摘要： The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

    摘要翻译： 本发明提供了一种半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化从SOI和体硅区域FET的组合构建的电路的功率和性能。

    Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
    4.
    发明授权
    Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement 有权
    用于自适应井偏置和功率和性能增强的混合晶体取向CMOS结构

    公开(公告)号：US07605429B2

    公开(公告)日：2009-10-20

    申请号：US11107611

    申请日：2005-04-15

    申请人： Kerry Bernstein ,  Jeffrey W. Sleight ,  Min Yang

    发明人： Kerry Bernstein ,  Jeffrey W. Sleight ,  Min Yang

    IPC分类号： H01L29/72

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

    摘要： The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

    摘要翻译： 本发明提供了一种半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化从SOI和体硅区域FET的组合构建的电路的功率和性能。

    Inactivity triggered self clocking logic family
    7.
    发明授权
    Inactivity triggered self clocking logic family 有权
    不活动触发自我计时逻辑家族

    公开(公告)号：US08575964B2

    公开(公告)日：2013-11-05

    申请号：US13426776

    申请日：2012-03-22

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0966 ,  H03K19/0013

    摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

    摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
    9.
    发明申请
    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT 有权
    用于冗余和改进的半导体芯片堆叠

    公开(公告)号：US20120326333A1

    公开(公告)日：2012-12-27

    申请号：US13607680

    申请日：2012-09-08

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    IPC分类号： H01L25/00

    CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

    摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。

    Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices
    10.
    发明授权
    Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
    用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管

    公开(公告)号：US08263472B2

    公开(公告)日：2012-09-11

    申请号：US13324486

    申请日：2011-12-13

    申请人： John E. Barth, Jr. ,  Kerry Bernstein

    发明人： John E. Barth, Jr. ,  Kerry Bernstein

    IPC分类号： H01L21/76

    CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

    摘要翻译： 半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层， 第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽 设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。