公开(公告)号：US11949022B2

公开(公告)日：2024-04-02

申请号：US17678971

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L29/788 ,  H01L21/285 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/788 ,  H01L21/28518 ,  H01L23/535 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US10651315B2

公开(公告)日：2020-05-12

申请号：US13716287

申请日：2012-12-17

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157 ,  H01L21/285 ,  H01L23/535 ,  H01L29/66 ,  H01L29/792

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US10083984B2

公开(公告)日：2018-09-25

申请号：US15679727

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H05K999/99

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US09773805B1

公开(公告)日：2017-09-26

申请号：US15187632

申请日：2016-06-20

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L29/51 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20160254159A1

公开(公告)日：2016-09-01

申请号：US15154467

申请日：2016-05-13

Applicant: Micron Technology, Inc.

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L21/28 ,  H01L21/764 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7889

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

Abstract translation: 各种实施例包括其形成装置和方法。 一种这样的设备可以包括第一介电材料和第二介电材料，以及在第一介电材料和第二介电材料之间的导电材料。 诸如浮动栅极或电荷阱的电荷存储元件位于第一介电材料和第二电介质材料之间并且与导电材料相邻。 电荷存储元件具有第一表面和第二表面。 第一和第二表面分别通过第一气隙和第二气隙与第一介电材料和第二电介质材料分开。 公开了附加的装置和方法。

公开(公告)号：US09343316B2

公开(公告)日：2016-05-17

申请号：US14825947

申请日：2015-08-13

Applicant: Micron Technology, Inc.

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7889

Abstract: Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a substrate. A conductive material is formed between the first dielectric material and the second dielectric material. An opening is formed through the first dielectric material, the second dielectric material, and the conductive material. The conductive material is recessed laterally from the opening to form a recessed control gate and to expose portions of the first dielectric material and the second dielectric material. Portions of a third dielectric material are formed over the exposed portions of the first dielectric material and the second dielectric material and a charge storage element is formed between the portions of the third dielectric material and adjacent to the recessed control gate. Portions of the third dielectric material are substantially removed. Additional methods, as well as apparatuses, are disclosed.

Abstract translation: 各种实施例包括形成存储器单元的方法。 在一个实施例中，在基板上形成第一电介质材料和第二电介质材料。 在第一介电材料和第二电介质材料之间形成导电材料。 通过第一介电材料，第二介电材料和导电材料形成开口。 导电材料从开口侧向凹入以形成凹入的控制栅极并暴露第一介电材料和第二介电材料的部分。 在第一介电材料和第二介电材料的暴露部分上形成第三电介质材料的一部分，并且电荷存储元件形成在第三电介质材料的部分之间并与凹陷控制栅极相邻。 基本上去除了第三绝缘材料的部分。 公开了附加的方法以及装置。