公开(公告)号：US20170263563A1

公开(公告)日：2017-09-14

申请号：US15601919

申请日：2017-05-22

Applicant: Micron Technology, Inc.

Inventor： Ashim Dutta ,  Mohd Kamran Akhtar ,  Shane J. Trapp

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/4821 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

公开(公告)号：US20250169069A1

公开(公告)日：2025-05-22

申请号：US19027756

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Troy R. Sorensen ,  Mohd Kamran Akhtar

IPC: H10B41/50 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27 ,  H10B43/50

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.

公开(公告)号：US11877434B2

公开(公告)日：2024-01-16

申请号：US16924995

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H10B12/00 ,  H01L21/3065

CPC classification number: H10B12/053 ,  H01L21/3065 ,  H10B12/34

Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

公开(公告)号：US11631684B2

公开(公告)日：2023-04-18

申请号：US17229672

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/112 ,  H01L21/67 ,  H01L21/3215 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10734395B2

公开(公告)日：2020-08-04

申请号：US16663068

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10700073B2

公开(公告)日：2020-06-30

申请号：US16419978

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US10347643B1

公开(公告)日：2019-07-09

申请号：US16002890

申请日：2018-06-07

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US09984977B2

公开(公告)日：2018-05-29

申请号：US15601919

申请日：2017-05-22

Applicant: Micron Technology, Inc.

Inventor： Ashim Dutta ,  Mohd Kamran Akhtar ,  Shane J. Trapp

IPC: H01L23/482 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/4821 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

公开(公告)号：US20180082940A1

公开(公告)日：2018-03-22

申请号：US15271924

申请日：2016-09-21

Applicant: Micron Technology, Inc.

Inventor： Troy R. Sorensen ,  Mohd Kamran Akhtar

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/115 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.

公开(公告)号：US12029032B2

公开(公告)日：2024-07-02

申请号：US18117989

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.