公开(公告)号：US20250103416A1

公开(公告)日：2025-03-27

申请号：US18909706

申请日：2024-10-08

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Kristen M. Hopper ,  Erika Prosser ,  Aaron P. Boehm

IPC: G06F11/07 ,  G06F1/20 ,  G06F1/30 ,  G06F3/06 ,  G06F11/30

Abstract: Methods, systems, and devices for persistent health monitoring for volatile memory devices are described. A memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. The memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. In some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. The memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.

公开(公告)号：US20240078153A1

公开(公告)日：2024-03-07

申请号：US18313670

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/102 ,  G06F11/1032

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US11682435B2

公开(公告)日：2023-06-20

申请号：US17811153

申请日：2022-07-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Debra M. Bell ,  Anthony D. Veches ,  James S. Rehmeyer ,  Libo Wang

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/406

CPC classification number: G11C7/22 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40603

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：US11550687B2

公开(公告)日：2023-01-10

申请号：US16707906

申请日：2019-12-09

Applicant: Micron Technology, Inc.

Inventor： Cheryl M. O'Donnell ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Debra M. Bell ,  Roya Baghi

IPC: G06F11/30 ,  G06F13/16 ,  G06F11/32 ,  B60H1/00

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, another device can be coupled to a memory device with an embedded sensor. The memory device can transmit a signal representing sensor data generated by the embedded sensor using a sensor output coupled to the other device. A controller coupled to a memory device may determine one or more threshold values of a sensor or sensors embedded in a memory device. The memory device may transmit an indication responsive to one or more sensors detecting a value greater or less than a threshold and may transmit the indication to another device.

公开(公告)号：US20220391334A1

公开(公告)日：2022-12-08

申请号：US17882550

申请日：2022-08-06

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/406 ,  G11C11/4096

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US20220334735A1

公开(公告)日：2022-10-20

申请号：US17856516

申请日：2022-07-01

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Naveh Malihi

IPC: G06F3/06 ,  G11C7/06

Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.

公开(公告)号：US11468939B2

公开(公告)日：2022-10-11

申请号：US17107306

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Debra M. Bell ,  Brian T. Pecha ,  Vaughn N. Johnson ,  Kyle Alexander

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to conditionally activate certain rows during refresh operations such that the memory devices can execute operations directed to the activated rows concurrently with the refresh operations. In some embodiments, the memory device receives an activate (ACT) command directed to a section of a memory bank while performing refresh operations for the memory bank. The memory device may carry out the ACT command if certain conditions are satisfied not to corrupt the data being refreshed. Subsequently, the memory device generates a signal to indicate the ACT command has been accepted to activate a row identified by the ACT command. Further, the memory device can perform subsequent access commands directed to the row, in parallel with the refresh operations.

公开(公告)号：US11422713B2

公开(公告)日：2022-08-23

申请号：US17157797

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Erika Prosser ,  Aaron P. Boehm ,  Debra M. Bell

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07

Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.

公开(公告)号：US20220129185A1

公开(公告)日：2022-04-28

申请号：US17518164

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Debra M. Bell

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

公开(公告)号：US20210295901A1

公开(公告)日：2021-09-23

申请号：US17338191

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.