公开(公告)号：US07253453B2

公开(公告)日：2007-08-07

申请号：US10442261

申请日：2003-05-21

Applicant: Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang

IPC: H01L21/336

CPC classification number: H01L27/0266

Abstract: An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.

Abstract translation: 一种用于提供静电放电保护的集成电路，其包括接触焊盘，包括具有衬底的晶体管的CMOS器件和用于提供耦合在所述接触焊盘和所述CMOS器件之间的静电放电保护的CDM钳位，所述CDM夹具包括至少一个 有源器件，其中CDM钳位将积聚在晶体管的衬底中的静电电荷传导到接触焊盘，并且其中CMOS器件耦合在高压线和低电压线之间。

公开(公告)号：US07092227B2

公开(公告)日：2006-08-15

申请号：US10230287

申请日：2002-08-29

Applicant: Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang

Inventor： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang

IPC: H02H9/00 ,  H02H3/22 ,  H01L27/01

CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection circuit includes a first terminal, a second terminal, an electrostatic discharge device coupled between the first and second terminals, and an active device coupled to the electrostatic discharge device and controlling an electrostatic current through the electrostatic discharge device. The electrostatic discharge device includes at least one of an SCR, an FOD, an active device, a BJT, and an MOS device.

Abstract translation: 静电放电保护电路包括第一端子，第二端子，耦合在第一和第二端子之间的静电放电装置，以及耦合到静电放电装置的有源装置，并且控制通过静电放电装置的静电电流。 静电放电装置包括SCR，FOD，有源器件，BJT和MOS器件中的至少一个。

公开(公告)号：US20050219780A1

公开(公告)日：2005-10-06

申请号：US11137173

申请日：2005-05-25

Applicant: Chyh-Yih Chang ,  Hsin-Chin Jiang ,  Ming-Dou Ker

Inventor： Chyh-Yih Chang ,  Hsin-Chin Jiang ,  Ming-Dou Ker

IPC: H01L23/58 ,  H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device for electrostatic discharge protection that includes a semiconductor substrate, a lightly doped region of a first dopant type formed in the substrate, a first diffusion region of the first dopant type formed at least partially in the lightly doped region, a second diffusion region of the first dopant type formed at least partially in the lightly doped region and spaced apart from the first diffusion region, a resistive path defined by the lightly doped region, the first and the second diffusion regions, and a third diffusion region of a second dopant type formed in the lightly doped region, and disposed between and spaced apart from the first and the second diffusion regions, wherein the third diffusion region keeps the resistive path at a low resistive state until a normal operation period occurs.

Abstract translation: 一种用于静电放电保护的集成电路装置，包括半导体衬底，形成在衬底中的第一掺杂剂类型的轻掺杂区域，至少部分形成在轻掺杂区域中的第一掺杂剂类型的第一扩散区，第二扩散 所述第一掺杂剂类型的区域至少部分地形成在所述轻掺杂区域中并且与所述第一扩散区间隔开;由所述轻掺杂区域，所述第一和第二扩散区域以及第二扩散区域的第三扩散区域限定的电阻路径 掺杂剂类型形成在轻掺杂区域中，并且设置在第一和第二扩散区域之间并与第一和第二扩散区域间隔开，其中第三扩散区域将电阻路径保持在低电阻状态直到发生正常操作周期。

公开(公告)号：US20050127445A1

公开(公告)日：2005-06-16

申请号：US11045300

申请日：2005-01-31

Applicant: Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

Inventor： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC: H01L21/336 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/01 ,  H01L27/02 ,  H01L31/0392 ,  H02H9/00

CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

Abstract translation: 一种静电放电保护装置，包括第一掺杂剂型的半导体衬底，形成在衬底中的至少一个第二掺杂剂型的源极/漏极对，其中源极/漏极对被分离以在其间限定沟道区域， 限定在源极/漏极对之间并且包括沟道区域的至少一部分的第一掺杂剂类型的掺杂区域，形成在衬底上的栅极电介质层以及形成在栅极介电层上方和沟道区域上方的栅极。

公开(公告)号：US06882009B2

公开(公告)日：2005-04-19

申请号：US10230055

申请日：2002-08-29

Applicant: Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

Inventor： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC: H01L21/265 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/07 ,  H01L29/10 ,  H01L21/01 ,  H01L23/62

CPC classification number: H01L27/0277 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0716 ,  H01L29/1079 ,  H01L29/1087 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

公开(公告)号：US06633087B2

公开(公告)日：2003-10-14

申请号：US09818455

申请日：2001-03-27

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L2940

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract translation: 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在层叠金属层中的每个金属层通过插塞与相邻的金属层耦合

公开(公告)号：US06465283B1

公开(公告)日：2002-10-15

申请号：US09654810

申请日：2000-09-05

Applicant: Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

Inventor： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

IPC: H01L21332

CPC classification number: H01L21/823814 ,  H01L21/823878 ,  H01L27/0921

Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

Abstract translation: 使用闭锁注入来提高CMOS电路中的闭锁抑制的结构和制造方法。 通过在寄生SCR的阴极和阳极上执行离子注入工艺来提高寄生SCR导通路径的阻抗，这可能引起闩锁现象。 因此，寄生SCR因此不容易以更高的抗噪声进行。 因此，可以提高闩锁抗扰度。 此外，可以进行离子注入工艺以实现防止闩锁效应的目的，而不消耗更多的布局面积，从而大大增强了电路设计的灵活性。

公开(公告)号：US06448641B2

公开(公告)日：2002-09-10

申请号：US09329648

申请日：1999-06-09

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L2312

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract translation: 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在堆叠金属层中的每个金属层通过插塞与相邻的金属层耦合。

公开(公告)号：US06335698B1

公开(公告)日：2002-01-01

申请号：US09414943

申请日：1999-10-08

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H03M136

CPC classification number: H03M1/361

Abstract: A flash analog-to-digital converter having a plurality of inverter circuits each comprising a programmable non-volatile memory cell and a load. The voltage values to be compared with the input voltage are threshold voltages individually programmable and stored on the plurality of memory cells. A comparison with the input voltage is performed by each of the memory cells, which are turned off to generate the value of logic “1” at an output when the input voltage is lower than the threshold voltage, and are turned on to generate the value of logic “0” at an output when the input voltage is greater than the threshold voltage.

Abstract translation: 一种具有多个逆变器电路的闪存模数转换器，每个逆变器电路各自包括可编程非易失性存储单元和负载。 要与输入电压进行比较的电压值是单独可编程并存储在多个存储单元上的阈值电压。 与输入电压的比较由每个存储单元执行，每个存储单元被关闭以在输入电压低于阈值电压时在输出端产生逻辑“1”的值，并被导通以产生该值 当输入电压大于阈值电压时，输出端的逻辑“0”。

公开(公告)号：US07989923B2

公开(公告)日：2011-08-02

申请号：US12342118

申请日：2008-12-23

Applicant: Tang-Kuei Tseng ,  Kun-Hsien Lin ,  Hsin-Chin Jiang

Inventor： Tang-Kuei Tseng ,  Kun-Hsien Lin ,  Hsin-Chin Jiang

IPC: H01L29/167

CPC classification number: H01L29/87

Abstract: A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.

Abstract translation: 公开了一种双向瞬态电压抑制装置。 双向瞬态电压抑制装置包括半导体管芯。 半导体管芯具有包括第一导电类型的半导体衬底，第二导电类型的掩埋层，外延层和五个扩散区域的多层结构。 掩埋层和半导体衬底形成第一半导体结。 第二导电类型的第一扩散区域和半导体衬底形成第二半导体结。 第一导电类型的第四扩散区域和第二导电类型的第三扩散区域形成第三半导体结。 第一导电类型的第五扩散区域和第二导电类型的第二扩散区域形成第四半导体结。