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公开(公告)号：US12126351B2
公开(公告)日：2024-10-22
申请号：US18061601
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Robert Rutten , Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H03M1/0621 , H03M1/1047 , H03M1/181 , H03M1/1009 , H03M1/68
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.
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公开(公告)号：US20240275365A1
公开(公告)日：2024-08-15
申请号：US18429939
申请日：2024-02-01
Applicant: NXP B.V.
Inventor： Gijsbert Willem Hardeman , Robert Rutten , Evert-Jan Daniel Pol , Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03H17/0294 , H03H17/0621 , H03H2017/0081
Abstract: A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.
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公开(公告)号：US12015426B2
公开(公告)日：2024-06-18
申请号：US17880868
申请日：2022-08-04
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/354
Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
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24.发明公开公开(公告)号：US20240048146A1
公开(公告)日：2024-02-08
申请号：US18357689
申请日：2023-07-24
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Lucien Johannes Breems , Robert Rutten , Mohammed Abo Alainein
IPC: H03M1/06
CPC classification number: H03M1/0602
Abstract: A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
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公开(公告)号：US20230361781A1
公开(公告)日：2023-11-09
申请号：US18310184
申请日：2023-05-01
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems , Pierluigi Cenci , Shagun Bajoria , Mohammed Abo Alainein
Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising:
i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13);
ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and
iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to:
swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).-
Patent Agency Ranking
26.发明授权公开(公告)号：US11463101B2
公开(公告)日：2022-10-04
申请号：US17158913
申请日：2021-01-26
Applicant: NXP B.V.
Inventor： Chenming Zhang , Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
Abstract: The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.
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公开(公告)号：US20170317860A1
公开(公告)日：2017-11-02
申请号：US15481038
申请日：2017-04-06
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H04L25/08 , H03M1/001 , H03M1/1009 , H04B1/0007 , H04B1/109 , H04B1/123
Abstract: A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.
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公开(公告)号：US09712184B2
公开(公告)日：2017-07-18
申请号：US15197398
申请日：2016-06-29
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
Abstract: A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.
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29.发明授权公开(公告)号：US11658677B2
公开(公告)日：2023-05-23
申请号：US17490415
申请日：2021-09-30
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Marcello Ganzerli , Chenming Zhang , Pierluigi Cenci
CPC classification number: H03M3/34 , H03M1/0626 , H03M1/0854 , H03M3/32 , H03M3/364 , H03M3/38
Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.
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30.发明申请公开(公告)号：US20230102232A1
公开(公告)日：2023-03-30
申请号：US17490415
申请日：2021-09-30
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Marcello Ganzerli , Chenming Zhang , Pierluigi Cenci
Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.
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