公开(公告)号：US07670929B2

公开(公告)日：2010-03-02

申请号：US11624070

申请日：2007-01-17

Applicant: Konstantin Bourdelle ,  Carlos Mazure ,  Olivier Rayssac ,  Pierre Rayssac, legal representative ,  Giséle Rayssac, legal representative

Inventor： Konstantin Bourdelle ,  Carlos Mazure ,  Olivier Rayssac

IPC: H01L21/30

CPC classification number: H01L21/187

Abstract: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.

Abstract translation: 本发明提供了直接接合基底的方法，其中至少一个包括在其前表面或其附近延伸的半导体材料层。 所提供的方法包括，在接合之前，使包含半导体材料的至少一个衬底的结合面在所选择的温度和选定的气体气氛中进行选择的热处理。 键合的衬底可用于电子，光学或光电子应用。

公开(公告)号：US07572331B2

公开(公告)日：2009-08-11

申请号：US11518366

申请日：2006-09-08

Applicant: Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

Inventor： Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

IPC: C30B25/18

CPC classification number: H01L21/0262 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract translation: 本发明涉及一种制造晶片的方法，该方法包括第一材料的单晶体体衬底和具有与第一材料的晶格不同的晶格的第二材料的至少一个外延层。 本发明提供了一种制造晶片的方法，其中可以以低成本以高效率和高质量在衬底上生长与衬底晶格失配的层。 包括粗糙化步骤以粗化本体衬底的表面，并且包括生长步骤，用于在粗糙表面上生长第二材料，数量较少的穿透位错和与外延生长的第二材料相比增强的应变松弛 抛光表面。

公开(公告)号：US08309431B2

公开(公告)日：2012-11-13

申请号：US10577175

申请日：2004-10-28

Applicant: Nguyet-Phuong Nguyen ,  Ian Cayrefourcq ,  Christelle Lagahe-Blanchard ,  Konstantin Bourdelle ,  Aurélie Tauzin ,  Franck Fournel

Inventor： Nguyet-Phuong Nguyen ,  Ian Cayrefourcq ,  Christelle Lagahe-Blanchard ,  Konstantin Bourdelle ,  Aurélie Tauzin ,  Franck Fournel

IPC: H01L21/46

CPC classification number: H01L21/76254

Abstract: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat treatment at a specified temperature during a specified period of time in order to create an embrittled buried area substantially at the specified depth without causing a thin layer, defined between the surface and the embrittled buried layer in relation to the remainder of the source-substrate, to become thermally detached. A controlled localized energy pulse is applied to the source-substrate in order to cause the self-supported detachment of the thin layer.

Abstract translation: 一种用于自支撑转移细层的方法，其中将至少一种离子注入相对于源 - 衬底表面的指定深度的源极 - 衬底中。 施加加强件以与源 - 基板紧密接触，并且源 - 基板在特定时间段内在特定温度下进行热处理，以便在基本上在指定深度处产生脆弱的掩埋区域而不产生薄层， 相对于源极 - 基板的其余部分，在表面和脆化的掩埋层之间限定为热分离。 将受控的局部能量脉冲施加到源 - 衬底，以引起薄层的自支撑分离。

公开(公告)号：US08309426B2

公开(公告)日：2012-11-13

申请号：US13093615

申请日：2011-04-25

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/76

CPC classification number: H01L21/76283 ,  H01L21/76275 ,  H01L29/66181

Abstract: The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.

Abstract translation: 本发明提供了在多层晶片中制造沟槽结构的方法，该多层晶片包括衬底，衬底上的氧化物层和氧化物层上的半导体层。 这些方法包括以下步骤：通过半导体层和氧化物层形成沟槽并延伸到衬底中，并且对所形成的沟槽进行退火处理，使得在沟槽的内表面处，半导体层的一些材料在 至少暴露在沟槽内表面的部分氧化物层的一部分。 根据本发明制造的衬底有利于制造各种半导体器件，例如MOSFET，沟槽电容器等。

公开(公告)号：US20110287571A1

公开(公告)日：2011-11-24

申请号：US13123661

申请日：2009-09-22

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L31/0376

CPC classification number: H01L27/14689 ,  H01L27/1464

Abstract: A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.

Abstract translation: 一种制造背照式图像传感器的方法，包括以下步骤：提供半导体层的第一衬底，特别是硅层，在半导体层上形成电子器件结构，然后仅仅掺杂半导体层。 通过这样做，可以实现改进的光电二极管的掺杂剂分布和电性能，使得最终产品，即图像传感器具有更好的质量。

公开(公告)号：US08058158B2

公开(公告)日：2011-11-15

申请号：US12726800

申请日：2010-03-18

Applicant: Konstantin Bourdelle ,  Bich-Yen Nguyen ,  Mariam Sadaka

Inventor： Konstantin Bourdelle ,  Bich-Yen Nguyen ,  Mariam Sadaka

IPC: H01L21/425 ,  H01L21/70

CPC classification number: H01L21/2007 ,  H01L21/187 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby, a higher number of process steps involved in the manufacturing process of hybrid semiconductor substrates may be avoided.

Abstract translation: 一种用于制造混合半导体衬底的方法包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和绝缘层上的SeOI层， 以及体半导体区域，其中所述SeOI区域和所述体半导体区域共享相同的基底基板; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。 因此，可以避免在混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

公开(公告)号：US20110241157A1

公开(公告)日：2011-10-06

申请号：US12793515

申请日：2010-06-03

Applicant: Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

IPC: H01L21/762 ,  H01L29/02

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.

Abstract translation: 本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案， 通过分子键合供体和手柄底物以获得供体 - 处理化合物。

公开(公告)号：US20100264458A1

公开(公告)日：2010-10-21

申请号：US12747099

申请日：2009-01-27

Applicant: Ionut Radu ,  Oleg Kononchuk ,  Konstantin Bourdelle

Inventor： Ionut Radu ,  Oleg Kononchuk ,  Konstantin Bourdelle

IPC: H01L29/02 ,  H01L21/26 ,  H01L21/71

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/76256

Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

Abstract translation: 一种用于电子，光学或光电子领域应用的异质结构的方法。 该方法包括在施主基板或接收器基板之一或两个基板上提供厚度小于或等于25纳米的氧化硅层，在900℃下热处理含有氧化硅层的基板 在含有氩或氢中的至少一种的中性或还原性气氛下，在至少1200℃，以在氧化硅内部形成层捕获通孔，在与氧化硅层的接合界面处将基板粘合在一起， 定位在它们之间，通过在25℃至500℃下退火衬底来加强接合，使得在接合界面处保留气体种类的捕获孔，并将作为施主衬底的一部分的活性层转移到接收器衬底上 以获得异质结构。

公开(公告)号：US07767545B2

公开(公告)日：2010-08-03

申请号：US11910104

申请日：2006-03-29

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/46 ,  H01L21/04

CPC classification number: H01L21/26506 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694

Abstract: A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method.

Abstract translation: 一种用于制造具有第一材料的顶层和其晶格参数不同于第一材料的第二材料的下层的衬底的方法。 该方法包括以下步骤：顶层的非晶化，以在位于暴露表面和非晶化界面之间的顶层中形成非晶区域，该界面下面的顶层部分被遮蔽以及非晶化，并保留为 晶体结构; 重结晶非晶区域同时也在界面处产生缺陷网络，其中网络形成与顶层的晶体结构的位错的边界，并且包含位于界面下方的顶层部分中的位错。 另外，通过该方法得到的基板。

公开(公告)号：US07645486B2

公开(公告)日：2010-01-12

申请号：US11677696

申请日：2007-02-22

Applicant: Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven R. A. Van Aerde ,  Marinus J. M. De Blank ,  Cornelius A. Van Der Jeugd

Inventor： Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven R. A. Van Aerde ,  Marinus J. M. De Blank ,  Cornelius A. Van Der Jeugd

IPC: C23C16/40

CPC classification number: H01L21/31612 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02271

Abstract: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapor deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600° C. and 1200° C., for a duration between 10 minutes and 6 hours.

Abstract translation: 本发明涉及一种制造低粗糙度的二氧化硅层的方法，其包括通过低压化学气相沉积（LPCVD）工艺在衬底上沉积二氧化硅层，该沉积工艺同时采用原硅酸四乙酯（TEOS ）作为膜沉积的源材料和与TEOS不反应的稀释气体流，使得稀释气体/ TEOS流量比在0.5和100之间; 并在600℃和1200℃之间的温度下将二氧化硅层退火10分钟至6小时。