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    METAL FILLING UNDER M1 LAYER OF SEMICONDUCTOR DEVICES
    21.
    发明申请
    METAL FILLING UNDER M1 LAYER OF SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210217697A1

    公开(公告)日：2021-07-15

    申请号：US16743350

    申请日：2020-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Bharani CHAVA ,  Stanley Seungchul SONG

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535

    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.

    HYBRID METAL INTERCONNECT STRUCTURES FOR ADVANCED PROCESS NODES
    22.
    发明申请
    HYBRID METAL INTERCONNECT STRUCTURES FOR ADVANCED PROCESS NODES 审中-公开

    公开(公告)号：US20190304919A1

    公开(公告)日：2019-10-03

    申请号：US15936964

    申请日：2018-03-27

    Applicant: QUALCOMM Incorporated

    Inventor： John ZHU ,  Da YANG ,  Stanley Seungchul SONG ,  Kern RIM

    IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

    Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a metal contact comprising a first hybrid interconnect structure disposed within a metallization layer, and a metal comprising a second hybrid interconnect structure disposed within the metallization layer, wherein each of the first and the second hybrid interconnect structures has a top portion and a bottom portion, and wherein the top portion of each of the first and the second hybrid interconnect structures comprises a metal element that is suitable for chemical mechanical planarization (CMP) and the bottom portion of each of the first and the second hybrid interconnect structures comprises ruthenium (Ru). The metal element may comprise cobalt (Co).

    STRUCTURE FOR COUPLING METAL LAYER INTERCONNECTS IN A SEMICONDUCTOR DEVICE
    24.
    发明申请
    STRUCTURE FOR COUPLING METAL LAYER INTERCONNECTS IN A SEMICONDUCTOR DEVICE 审中-公开
    用于在半导体器件中耦合金属层互连的结构

    公开(公告)号：US20160343661A1

    公开(公告)日：2016-11-24

    申请号：US15159744

    申请日：2016-05-19

    Applicant: QUALCOMM Incorporated

    Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Stanley Seungchul SONG ,  Kern RIM ,  John Jianhong ZHU

    IPC: H01L23/535 ,  H01L27/092 ,  H01L29/45 ,  H01L27/02

    CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L27/0207

    Abstract: A MOS device includes a first interconnect extending in a first direction, the first interconnect being configured in a metal layer. The MOS device further includes a second interconnect extending in the first direction parallel to the first interconnect, the second interconnect being configured in the metal layer. The MOS device further includes a gate interconnect extending in a second direction orthogonal to the first direction, the gate interconnect being situated in a first layer below the metal layer, wherein the gate interconnect is coupled to the first interconnect by a first via. The MOS device further includes a third interconnect extending in the second direction, the third interconnect being coupled to both the first and second interconnects, wherein the third interconnect is coupled to the first interconnect by a second via, and wherein the second via contacts the first via.

    Abstract translation: MOS器件包括沿第一方向延伸的第一互连，第一互连配置在金属层中。 MOS器件还包括在第一方向上平行于第一互连延伸的第二互连，第二互连配置在金属层中。 MOS器件还包括在与第一方向正交的第二方向上延伸的栅极互连，栅极互连位于金属层下方的第一层中，其中栅极互连通过第一通孔耦合到第一互连。 MOS器件还包括在第二方向上延伸的第三互连，第三互连件耦合到第一和第二互连件，其中第三互连通过第二通孔耦合到第一互连，并且其中第二通孔接触第一互连 通过。

    SEVEN-TRANSISTOR STATIC RANDOM-ACCESS MEMORY BITCELL WITH REDUCED READ DISTURBANCE
    27.
    发明申请
    SEVEN-TRANSISTOR STATIC RANDOM-ACCESS MEMORY BITCELL WITH REDUCED READ DISTURBANCE 审中-公开
    具有减少读取干扰的七电极静态随机存取存储器

    公开(公告)号：US20160093365A1

    公开(公告)日：2016-03-31

    申请号：US14499149

    申请日：2014-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul SONG ,  Seong-Ook JUNG ,  Young Hwi YANG ,  Zhongze WANG ,  Choh Fei YEAP

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

    Abstract translation: 系统和方法涉及七晶体管静态随机存取存储器（7T SRAM）位单元，其包括具有第一上拉晶体管，第一下拉晶体管和第一存储节点的第一反相器，以及具有 第二上拉晶体管，第二下拉晶体管和第二存储节点。 第二存储节点耦合到第一上拉晶体管和第一下拉晶体管的栅极。 传输门被配置为在写入操作，待机模式和保持模式期间将第一存储节点选择性地耦合到第二上拉晶体管和第二下拉晶体管的栅极，并且选择性地将第一存储节点与 在读取操作期间第一上拉晶体管的栅极和第一下拉晶体管。 可以通过耦合到第一存储节点的存取晶体管来读取或写入7T SRAM位单元。

    HIGH DENSITY STATIC RANDOM ACCESS MEMORY ARRAY HAVING ADVANCED METAL PATTERNING
    28.
    发明申请
    HIGH DENSITY STATIC RANDOM ACCESS MEMORY ARRAY HAVING ADVANCED METAL PATTERNING 有权
    高密度静态随机访问存储阵列具有高级金属图案

    公开(公告)号：US20150333131A1

    公开(公告)日：2015-11-19

    申请号：US14281710

    申请日：2014-05-19

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

    IPC: H01L29/40 ,  H01L29/161 ,  H01L27/11

    CPC classification number: H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

    Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

    Abstract translation: 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二相对侧对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。

    VIA MATERIAL SELECTION AND PROCESSING
    29.
    发明申请
    VIA MATERIAL SELECTION AND PROCESSING 有权
    通过材料选择和处理

    公开(公告)号：US20150325515A1

    公开(公告)日：2015-11-12

    申请号：US14274470

    申请日：2014-05-09

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong ZHU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

    Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

    REDUCED HEIGHT M1 METAL LINES FOR LOCAL ON-CHIP ROUTING
    30.
    发明申请
    REDUCED HEIGHT M1 METAL LINES FOR LOCAL ON-CHIP ROUTING 有权
    降低高度M1金属线用于本地片上路由

    公开(公告)号：US20150262930A1

    公开(公告)日：2015-09-17

    申请号：US14206360

    申请日：2014-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

    Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

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