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    Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors
    21.
    发明授权
    Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors 有权
    用于增强应力传递到NMOS和PMOS晶体管的沟道区域的技术

    公开(公告)号：US07344984B2

    公开(公告)日：2008-03-18

    申请号：US11468450

    申请日：2006-08-30

    申请人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

    发明人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

    摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

    摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。

    Methods of Forming Metal Silicide Regions on Semiconductor Devices
    22.
    发明申请
    Methods of Forming Metal Silicide Regions on Semiconductor Devices 有权
    在半导体器件上形成金属硅化物区域的方法

    公开(公告)号：US20130157450A1

    公开(公告)日：2013-06-20

    申请号：US13331842

    申请日：2011-12-20

    申请人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    发明人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/66545

    摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

    摘要翻译： 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域， 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

    Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas
    24.
    发明申请
    Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas 有权
    包括高K金属栅电极结构的互补晶体管和排水和源区域中的外延形成的半导体材料

    公开(公告)号：US20120211838A1

    公开(公告)日：2012-08-23

    申请号：US13370944

    申请日：2012-02-10

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy forN-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

    摘要翻译： 当形成包括具有减小的栅极长度的互补晶体管的复杂半导体器件时，可以基于单独提供的半导体合金（例如用于P沟道晶体管的硅/锗合金）和用于磷/磷半导体合金的硅/磷半导体合金 N沟道晶体管。 为此，可以应用优异的硬掩模图案化方案，以提供与复杂的替代栅极方法的兼容性，同时避免不适当的工艺不均匀性，特别是关于去除电介质盖层。

    Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material
    25.
    发明申请
    Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material 有权
    通过盖层去除形成的复杂的门极电极结构，减少嵌入式应变诱导半导体材料的损耗

    公开(公告)号：US20120196417A1

    公开(公告)日：2012-08-02

    申请号：US13358101

    申请日：2012-01-25

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.

    摘要翻译： 当形成诸如高k金属栅电极结构的复杂的栅电极结构时，可以实现适当的封装，同时也可以避免在一种晶体管中提供的应变诱导半导体材料的不适当的材料损耗。 为此，可以在沉积应变诱导半导体材料之前对保护间隔物结构进行图案化，其基于相同的工艺流程，对于每种类型的晶体管，在应变诱导半导体材料沉积之后， 可以提供蚀刻停止层，以便保持活性区域的完整性。