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127 条记录 (耗时 0.036 秒)

    METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE
    24.
    发明申请
    METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE 有权
    形成分离栅存储器件的方法

    公开(公告)号：US20080199996A1

    公开(公告)日：2008-08-21

    申请号：US11676403

    申请日：2007-02-19

    申请人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    发明人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

    摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

    摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中在牺牲隔离物上形成的纳米团簇被去除并且其它纳米团簇保留。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

    METHOD OF FORMING A MULTI-BIT NONVOLATILE MEMORY DEVICE
    27.
    发明申请
    METHOD OF FORMING A MULTI-BIT NONVOLATILE MEMORY DEVICE 有权
    形成多位非易失性存储器件的方法

    公开(公告)号：US20080182377A1

    公开(公告)日：2008-07-31

    申请号：US11668210

    申请日：2007-01-29

    申请人： Rajesh A. Rao ,  Ramachandran Muralidhar

    发明人： Rajesh A. Rao ,  Ramachandran Muralidhar

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/66772 ,  H01L29/7887

    摘要： In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.

    摘要翻译： 在制造多位存储单元时，在半导体衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 一层栅极材料形成在第二绝缘层之上并图案化以留下栅极部分。 蚀刻第二绝缘层以切割栅极部分，并将第二绝缘层的一部分留在第一绝缘层和栅极部分之间。 在第一绝缘层上形成纳米晶体。 纳米晶体的第一部分在第二绝缘层部分的第一侧上的栅极部分下方，并且纳米晶体的第二部分在第二绝缘层部分的第二侧上的栅极部分下方。 纳米晶体的第一和第二部分分别用于存储第一和第二位的逻辑状态。

    Transistor having three electrically isolated electrodes and method of formation
    28.
    发明授权
    Transistor having three electrically isolated electrodes and method of formation 有权
    具有三个电隔离电极的晶体管和形成方法

    公开(公告)号：US07098502B2

    公开(公告)日：2006-08-29

    申请号：US10705317

    申请日：2003-11-10

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L27/108 ,  H01L27/12 ,  H01L21/00 ,  H01L21/336

    CPC分类号： H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

    摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

    摘要翻译： 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

    Transistor with vertical dielectric structure
    29.
    发明授权
    Transistor with vertical dielectric structure 有权
    具有垂直电介质结构的晶体管

    公开(公告)号：US07018876B2

    公开(公告)日：2006-03-28

    申请号：US10871772

    申请日：2004-06-18

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7887

    摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.

    摘要翻译： 一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。 半导体结构包括沟道区（731）和源极/漏极区（707,709）。 晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。 在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。 在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。

    Method for forming a memory structure using a modified surface topography and structure thereof
    30.
    发明授权
    Method for forming a memory structure using a modified surface topography and structure thereof 有权
    使用改性表面形貌及其结构形成记忆结构的方法

    公开(公告)号：US06991984B2

    公开(公告)日：2006-01-31

    申请号：US10765804

    申请日：2004-01-27

    申请人： Paul A. Ingersoll ,  Gowrishankar L. Chindalore ,  Ramachandran Muralidhar

    发明人： Paul A. Ingersoll ,  Gowrishankar L. Chindalore ,  Ramachandran Muralidhar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4925 ,  H01L29/4958

    摘要： To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

    摘要翻译： 为了增加半导体器件10的栅极耦合比，离散元件22（例如纳米晶体）沉积在浮动栅极16上。 在一个实施例中，分立元件22预先形成为气相并且通过静电力附着到半导体器件10。 在一个实施例中，分立元件22预先形成在不同于它们附接的腔室的腔室中。 在另一个实施例中，相同的室用于整个沉积工艺。 可选的界面层17可以形成在浮动栅极16和离散元件22之间。