公开(公告)号：US09053931B2

公开(公告)日：2015-06-09

申请号：US13626265

申请日：2012-09-25

申请人： Hisashi Yoshida ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

发明人： Hisashi Yoshida ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

IPC分类号： H01L21/02 ,  H01L29/10 ,  H01L29/205 ,  H01L33/32 ,  H01L33/06

CPC分类号： H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262

摘要： According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)−Wi)/Wi≦0.008.

摘要翻译： 根据一个实施例，氮化物半导体晶片包括：硅衬底; 设置在所述硅基板上的缓冲部; 以及设置在缓冲部上并包含氮化物半导体的功能层。 缓冲部包括含有氮化物半导体的第一〜第n缓冲层（n为4以上的整数）。 第一至第n缓冲层的第i个缓冲层（i为1以上且小于n的整数）在平行于第一缓冲层的主面的第一方向上具有晶格长度Wi。 设置在第i个缓冲层上的第（i + 1）个缓冲层在第一方向上具有晶格长度W（i + 1）。 在第一至第n缓冲层中，第i个缓冲层和第（i + 1）个缓冲层满足关系式（W（i + 1）-Wi）/ W i＆nlE; 0。008。

公开(公告)号：US20140061693A1

公开(公告)日：2014-03-06

申请号：US13626265

申请日：2012-09-25

申请人： Hisashi YOSHIDA ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

发明人： Hisashi YOSHIDA ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

IPC分类号： H01L31/0304 ,  H01L21/20 ,  H01L29/205

CPC分类号： H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262

摘要： According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)−Wi)/Wi≦0.008.

摘要翻译： 根据一个实施例，氮化物半导体晶片包括：硅衬底; 设置在所述硅基板上的缓冲部; 以及设置在缓冲部上并包含氮化物半导体的功能层。 缓冲部包括含有氮化物半导体的第一〜第n缓冲层（n为4以上的整数）。 第一至第n缓冲层的第i个缓冲层（i为1以上且小于n的整数）在平行于第一缓冲层的主面的第一方向上具有晶格长度Wi。 设置在第i个缓冲层上的第（i + 1）个缓冲层在第一方向上具有晶格长度W（i + 1）。 在第一至第n缓冲层中，第i个缓冲层和第（i + 1）个缓冲层满足关系式（W（i + 1）-Wi）/ Wi0.008。

公开(公告)号：US08815717B2

公开(公告)日：2014-08-26

申请号：US12875835

申请日：2010-09-03

申请人： Yoshiyuki Harada ,  Koichi Tachibana ,  Toshiki Hikosaka ,  Hajime Nago ,  Shinya Nunoue

发明人： Yoshiyuki Harada ,  Koichi Tachibana ,  Toshiki Hikosaka ,  Hajime Nago ,  Shinya Nunoue

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： C23C16/45504 ,  C23C16/303 ,  C23C16/45574 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.

摘要翻译： 根据一个实施例，公开了一种通过提供III族源材料气体和V族原料气体在衬底上形成氮化物半导体层的气相沉积方法。 该方法可以通过从第一出口提供III族源材料气体并且通过提供第V族源极材料来沉积包括具有不小于10原子％的III族元素中Al的组分比例的氮化物半导体的第一半导体层， 来自第二出口的原料气体。 该方法可以通过混合第III族和第V族源材料气体并将第III族和V族源混合，从而沉积包含具有小于10原子％的III族元素中的Al的组分比例的氮化物半导体的第二半导体层 - 来自第一出口和第二出口中的至少一个的材料气体。

公开(公告)号：US20130234106A1

公开(公告)日：2013-09-12

申请号：US13601454

申请日：2012-08-31

申请人： Naoharu Sugiyama ,  Taisuke Sato ,  Kotaro Zaima ,  Jumpei Tajima ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Hisashi Yoshida ,  Shinya Nunoue

发明人： Naoharu Sugiyama ,  Taisuke Sato ,  Kotaro Zaima ,  Jumpei Tajima ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Hisashi Yoshida ,  Shinya Nunoue

IPC分类号： H01L33/12

CPC分类号： H01L33/32 ,  H01L33/06 ,  H01L33/12

摘要： According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.

摘要翻译： 根据一个实施例，半导体发光器件包括：包含氮化物半导体晶体并且在（0001）表面中具有拉伸应力的第一导电类型的第一半导体层; 含有氮化物半导体晶体并在（0001）表面具有拉伸应力的第二导电类型的第二半导体层; 设置在所述第一半导体层和所述第二半导体层之间的包含氮化物半导体晶体并且具有大于所述第一半导体层的晶格常数的平均晶格常数的发光层; 以及第一应力施加层，其设置在与所述第一半导体层的所述发光层相对的一侧上，并向所述第一半导体层施加压缩应力。

公开(公告)号：US08093083B1

公开(公告)日：2012-01-10

申请号：US13029416

申请日：2011-02-17

申请人： Toshiki Hikosaka ,  Tomonari Shioda ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Koichi Tachibana ,  Shinya Nunoue

发明人： Toshiki Hikosaka ,  Tomonari Shioda ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Koichi Tachibana ,  Shinya Nunoue

IPC分类号： H01L21/00 ,  H01L33/00

CPC分类号： H01L33/007 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262

摘要： In one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The device includes a crystal layer including a nitride semiconductor. The crystal layer contains In and Ga atoms. The method can include forming the crystal layer by supplying a source gas including a first molecule including Ga atoms and a second molecule including In atoms onto a base body. The crystal layer has a ratio xs of a number of the In atoms to a total of the In atoms and the Ga atoms being not less than 0.2 and not more than 0.4. A vapor phase supply ratio xv of In is a ratio of a second partial pressure to a total of first and second partial pressures. The first and second partial pressures are pressure of the first and second molecules and degradation species of the first and second molecules on the source gas, respectively. (1−1/xv)/(1−1/xs) is less than 0.1.

摘要翻译： 在一个实施例中，公开了一种用于制造半导体发光器件的方法。 该器件包括包含氮化物半导体的晶体层。 晶体层含有In和Ga原子。 该方法可以包括通过将包括Ga原子的第一分子和包括In原子的第二分子的源气体供应到基体上来形成晶体层。 晶体层的In原子数与In原子的总和的比xs和Ga原子的比率不小于0.2且不大于0.4。 In的气相供给比xv是第二分压与第一和第二分压的总和的比。 第一和第二分压分别是源气体上的第一和第二分子的压力和第一和第二分子的降解物质。 （1-1 / xv）/（1-1 / xs）小于0.1。

公开(公告)号：US20140084296A1

公开(公告)日：2014-03-27

申请号：US13729713

申请日：2012-12-28

申请人： Hisashi YOSHIDA ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

发明人： Hisashi YOSHIDA ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

IPC分类号： H01L29/20 ,  H01L21/02

CPC分类号： H01L29/2003 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/7786 ,  H01L33/007 ,  H01L33/12

摘要： A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.

摘要翻译： 氮化物半导体晶片包括硅衬底，堆叠多层单元，含硅单元和上层单元。 硅衬底具有主表面。 堆叠的多层单元设置在主表面上。 堆叠的多层单元包括N个缓冲层。 缓冲层包括第i个缓冲层和设置在第i个缓冲层上的第（i + 1）个缓冲层。 第i个缓冲层在平行于主表面的第一方向上具有第i个晶格长度Wi。 第（i + 1）个缓冲层在第一方向具有第（i + 1）个格子长度W（i + 1）。 对于所有缓冲层，满足（W（i + 1）-Wi）/ Wi＆nlE; 0.008的关系。 含硅单元设置在堆叠的多层单元上。 上层单元设置在含硅单元上。

公开(公告)号：US08610106B2

公开(公告)日：2013-12-17

申请号：US13213821

申请日：2011-08-19

申请人： Tomonari Shioda ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

发明人： Tomonari Shioda ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Naoharu Sugiyama ,  Shinya Nunoue

IPC分类号： H01L33/06

CPC分类号： H01L33/40 ,  H01L33/06 ,  H01L33/32

摘要： According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting part. The light emitting part is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, a first n-side intermediate layer and a first p-side intermediate layer. The barrier layer, the well layer, the n-side layer and the p-side intermediate layer include a nitride semiconductor. An In composition ratio in the n-side layer decreases along a first direction from the n-type layer toward the p-type layer. An In composition ratio in the p-side layer decreases along the first direction. An average change rate of the In ratio in the p-side layer is lower than an average change rate of the In ratio in the n-side layer.

摘要翻译： 根据一个实施例，半导体发光器件包括n型半导体层，p型半导体层和发光部分。 发光部分设置在n型半导体层和p型半导体层之间，并且包括第一发光层。 第一发光层包括第一阻挡层，第一阱层，第一n侧中间层和第一p侧中间层。 阻挡层，阱层，n侧层和p侧中间层包括氮化物半导体。 n侧层的An组成比沿着从n型层向p型层的第一方向减小。 P侧层的In组成比沿着第一方向减小。 p侧的In比的平均变化率低于n侧层的In比的平均变化率。

公开(公告)号：US08598605B2

公开(公告)日：2013-12-03

申请号：US13601454

申请日：2012-08-31

申请人： Naoharu Sugiyama ,  Taisuke Sato ,  Kotaro Zaima ,  Jumpei Tajima ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Hisashi Yoshida ,  Shinya Nunoue

发明人： Naoharu Sugiyama ,  Taisuke Sato ,  Kotaro Zaima ,  Jumpei Tajima ,  Toshiki Hikosaka ,  Yoshiyuki Harada ,  Hisashi Yoshida ,  Shinya Nunoue

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/32 ,  H01L33/06 ,  H01L33/12

摘要： According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.

摘要翻译： 根据一个实施例，半导体发光器件包括：包含氮化物半导体晶体并且在（0001）表面中具有拉伸应力的第一导电类型的第一半导体层; 含有氮化物半导体晶体并在（0001）表面具有拉伸应力的第二导电类型的第二半导体层; 设置在所述第一半导体层和所述第二半导体层之间的包含氮化物半导体晶体并且具有大于所述第一半导体层的晶格常数的平均晶格常数的发光层; 以及第一应力施加层，其设置在与所述第一半导体层的所述发光层相对的一侧上，并向所述第一半导体层施加压缩应力。

公开(公告)号：US08525197B2

公开(公告)日：2013-09-03

申请号：US13035304

申请日：2011-02-25

申请人： Yoshiyuki Harada ,  Toshiki Hikosaka ,  Tomonari Shioda ,  Koichi Tachibana ,  Hajime Nago ,  Shinya Nunoue

发明人： Yoshiyuki Harada ,  Toshiki Hikosaka ,  Tomonari Shioda ,  Koichi Tachibana ,  Hajime Nago ,  Shinya Nunoue

IPC分类号： H01L31/072

CPC分类号： H01L33/08 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/06

摘要： According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.

摘要翻译： 根据一个实施例，半导体发光器件包括n型半导体层，p型半导体层和设置在其间的发光部分。 发光部分包括多个发光层。 每个发光层包括在垂直于从n型半导体层朝向p型半导体层的第一方向的平面中与阱层区域并置的阱层区域和非阱层区域。 每个阱层区域具有常见的An In组成比。 每个阱层区域包括在垂直于第一方向的方向上具有50纳米或更大的宽度的部分。

公开(公告)号：US20130087761A1

公开(公告)日：2013-04-11

申请号：US13405565

申请日：2012-02-27

申请人： Shigeya KIMURA ,  Yoshiyuki Harada ,  Hajime Nago ,  Koichi Tachibana ,  Shinya Nunoue

发明人： Shigeya KIMURA ,  Yoshiyuki Harada ,  Hajime Nago ,  Koichi Tachibana ,  Shinya Nunoue

IPC分类号： H01L33/06

CPC分类号： H01L33/06 ,  B82Y20/00 ,  H01L33/12 ,  H01L33/32 ,  H01S5/3408 ,  H01S5/34333

摘要： According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers containing a nitride semiconductor and a light emitting layer. The emitting layer includes a barrier layer containingIII group elements, and a well layer stacked with the barrier layer and containing III group elements. The barrier layer is divided into a first portion on an n-type semiconductor layer side and a second portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the second portion is lower than that of the first portion. The well layer is divided into a third portion on an n-type semiconductor layer side and a fourth portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the fourth portion is higher than that of the third portion.