公开(公告)号：US06787475B2

公开(公告)日：2004-09-07

申请号：US10163812

申请日：2002-06-05

申请人： Zhuxu Wang ,  Jingbao Liu ,  Claes H. Bjorkman ,  Bryan Pu

发明人： Zhuxu Wang ,  Jingbao Liu ,  Claes H. Bjorkman ,  Bryan Pu

IPC分类号： H01L21302

CPC分类号： H01L21/31116

摘要： A dielectric plasma etch method particularly useful for assuring that residue does not form in large open pad areas used for monitoring etching of narrow via and contact holes. The main dielectric etch of the via and contact holes uses a highly polymerizing chemistry, preferably of a low-F/C fluorocarbon such as C4F6 in conjunction with O2 and Ar. A short flash step precedes the main plasma etch using a plasma of a gas less polymerizing than the gas of the main etch, and the plasma is not extinguished between the flash and main steps. The flash step may be used to remove an anti-reflection coating (ARC) covering the dielectric layer and use a lean fluorocarbon, such as CF4, perhaps together with O2 and Ar. In the absence of ARC, an argon flash may be used.

摘要翻译： 介质等离子体蚀刻方法特别适用于确保在用于监测窄通孔和接触孔蚀刻的大开孔焊盘区域中不形成残留物。 通孔和接触孔的主电介质蚀刻使用高度聚合的化学物质，优选低F / C碳氟化合物，例如与O 2和Ar结合的C 4 F 6。 使用比主蚀刻的气体少的聚合气体的等离子体进行主等离子体蚀刻之前的短闪光步骤，并且在闪光和主要步骤之间的等离子体不会熄灭。 闪光步骤可以用于除去覆盖介电层的抗反射涂层（ARC），并且可以与O 2和Ar一起使用诸如CF 4的贫碳氟化合物。 在没有ARC的情况下，可以使用氩气闪光。

公开(公告)号：US08840725B2

公开(公告)日：2014-09-23

申请号：US12884978

申请日：2010-09-17

申请人： David Palagashvili ,  Michael D. Willwerth ,  Alex Erenstein ,  Jingbao Liu

发明人： David Palagashvili ,  Michael D. Willwerth ,  Alex Erenstein ,  Jingbao Liu

IPC分类号： C23C16/455 ,  C23C16/50 ,  C23C16/509 ,  C23F1/00 ,  H01L21/306 ,  H01J37/32 ,  C23C16/06 ,  C23C16/22

CPC分类号： H01J37/32449 ,  H01J37/32091 ,  H01J37/32816 ,  H01J37/32844

摘要： Embodiments of the present invention provide a recursive liner system that facilitates providing more uniform flow of gases proximate the surface of a substrate disposed within an apparatus for processing a substrate (e.g., a process chamber). In some embodiments, a recursive liner system may include an outer liner having an outer portion configured to line the walls of a process chamber, a bottom portion extending inward from the outer portion, and a lip extending up from the bottom portion to define a well; and an inner liner having a lower portion configured to be at least partially disposed in the well to define, together with the outer liner, a recursive flow path therebetween.

摘要翻译： 本发明的实施例提供了一种循环衬垫系统，其有助于提供更接近于布置在用于处理衬底（例如，处理室）的设备内的衬底的表面的气体的均匀流动。 在一些实施例中，递归衬垫系统可以包括具有外部部分的外部衬套，所述外部部分被配置为对准处理室的壁，从外部向内延伸的底部，以及从底部向上延伸以限定孔 ; 以及内衬，其具有被配置为至少部分地设置在所述孔中的下部，以与所述外衬垫一起限定其间的递归流动路径。

公开(公告)号：US20140034241A1

公开(公告)日：2014-02-06

申请号：US14051340

申请日：2013-10-10

申请人： Sergy G. Belostotskiy ,  Michael G. Chafin ,  Jingbao Liu ,  David Palagashvili

发明人： Sergy G. Belostotskiy ,  Michael G. Chafin ,  Jingbao Liu ,  David Palagashvili

IPC分类号： H01J37/20

CPC分类号： H01J37/20 ,  H01J37/32715 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/67109 ,  H01L21/6831

摘要： Methods and systems for temperature enhanced chucking and dechucking of resistive substrates in a plasma processing apparatus are described herein. In certain embodiments, methods and systems incorporate modulating a glass carrier substrate temperature during a plasma etch process to chuck and dechuck the carrier at first temperatures elevated relative to second temperatures utilized during plasma etching. In embodiments, one or more of plasma heat, lamp heat, resistive heat, and fluid heat transfer are controlled to modulate the carrier substrate temperature between chucking temperatures and process temperatures with each run of the plasma etch process.

摘要翻译： 本文描述了用于等离子体处理装置中的电阻衬底的温度升高夹持和脱扣的方法和系统。 在某些实施方案中，方法和系统包括在等离子体蚀刻工艺期间调节玻璃载体衬底温度，以在相对于在等离子体蚀刻期间使用的第二温度升高的第一温度下卡住和剥离载体。 在实施例中，控制等离子体热，灯热，电阻热和流体热传递中的一种或多种，​​以在等离子体蚀刻工艺的每次运行中调制夹持温度和工艺温度之间的载体衬底温度。

公开(公告)号：US20070243714A1

公开(公告)日：2007-10-18

申请号：US11406000

申请日：2006-04-18

申请人： Taeho Shin ,  Jingbao Liu ,  Ajey Joshi ,  Jong Kim ,  Wei-Te Wu

发明人： Taeho Shin ,  Jingbao Liu ,  Ajey Joshi ,  Jong Kim ,  Wei-Te Wu

IPC分类号： H01L21/461 ,  C03C15/00

CPC分类号： H01L21/76802 ,  H01L21/31122 ,  H01L21/31144

摘要： A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at least one fluorine-containing cleaning agent species is added to already present etchant species of said continuous etching process for a limited time period, wherein the length of time of each cleaning step ranges from about 5% to about 100% of the time length of an etch step which either precedes or follows said cleaning step.

摘要翻译： 在将所述凹入特征等离子体蚀刻到半导体衬底中的含碳层中时，从导通凹陷特征的开口去除含硅的硬质聚合物材料的方法。 该方法包括在连续蚀刻过程中间歇地使用清洁步骤，其中在有限时间段内将至少一种含氟清洁剂种类添加到已存在的所述连续蚀刻工艺的蚀刻剂物质中，其中时间长度 每个清洁步骤的范围是在所述清洁步骤之前或之后的蚀刻步骤的时间长度的约5％至约100％。

公开(公告)号：US07105442B2

公开(公告)日：2006-09-12

申请号：US10154532

申请日：2002-05-22

申请人： Hongching Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Hong D. Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

发明人： Hongching Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Hong D. Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

IPC分类号： H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31144 ,  G03F7/40 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3146

摘要： A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer. Substructures formed in the fabrication process are also described. Spacers are also shown to be favorably employed in making feature-in-feature structures.

摘要翻译： 描述了一种降低集成电路特征的关键尺寸的方法，其中以典型特征蚀刻的方式沉积，图案化和打开第一掩模层（101），并且在蚀刻之前沉积第二掩模层（201） 底层绝缘子。 有利地以基本上共形的方式涂覆第二掩模层。 打开第二掩蔽层，同时将第二层的材料留在第一掩模层的侧壁上作为间隔物导致下层绝缘体中的特征临界尺寸的减小。 包括无定形碳和有机材料在内的可湿性掩蔽材料可以不经CMP去除，从而降低成本。 利用形成间隔物的最上面的掩模层（302）下方的多于一个掩模层（101,301）也可获得有利的结果。 还描述了其中斜率蚀刻替代单独的间隔层的添加的实施例。 还描述了在制造过程中形成的子结构。 垫片也被用于制造特征特征结构。

公开(公告)号：US20050090118A1

公开(公告)日：2005-04-28

申请号：US10823364

申请日：2004-04-12

申请人： Steven Shannon ,  Dennis Grimard ,  Theodoros Panagopoulos ,  Daniel Hoffman ,  Michael Chafin ,  Troy Detrick ,  Alexander Paterson ,  Jingbao Liu ,  Taeho Shin ,  Bryan Pu

发明人： Steven Shannon ,  Dennis Grimard ,  Theodoros Panagopoulos ,  Daniel Hoffman ,  Michael Chafin ,  Troy Detrick ,  Alexander Paterson ,  Jingbao Liu ,  Taeho Shin ,  Bryan Pu

IPC分类号： H01L21/3065 ,  H01J37/32 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01J37/32082 ,  H01J37/32165

摘要： A method and apparatus for controlling characteristics of a plasma in a semiconductor substrate processing chamber using a dual frequency RF source is provided. The method comprises supplying a first RF signal to a first electrode disposed in a processing chamber, and supplying a second RF signal to the first electrode, wherein an interaction between the first and second RF signals is used to control at least one characteristic of a plasma formed in the processing chamber.

摘要翻译： 提供一种使用双频RF源控制半导体衬底处理室中的等离子体特性的方法和装置。 该方法包括向设置在处理室中的第一电极提供第一RF信号，并向第一电极提供第二RF信号，其中第一和第二RF信号之间的相互作用用于控制等离子体的至少一个特性 形成在处理室中。