公开(公告)号：US07479677B2

公开(公告)日：2009-01-20

申请号：US12020266

申请日：2008-01-25

申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

公开(公告)号：US07211866B2

公开(公告)日：2007-05-01

申请号：US11111129

申请日：2005-04-20

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Yupin K. Fong ,  George Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Yupin K. Fong ,  George Samachisa

IPC分类号： H01L27/01

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/7887

摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.

摘要翻译： 通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路 个别浮动门。 衬底中的电荷源和漏极扩散在整个行上连续伸长。 沉积在浮动栅极行之间的场电介质在行之间提供电隔离。 可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。 在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。 包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。 其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

公开(公告)号：US06977844B2

公开(公告)日：2005-12-20

申请号：US11054084

申请日：2005-02-08

申请人： Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

发明人： Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

IPC分类号： G11C16/02 ,  G11C16/12 ,  G11C16/04

CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

摘要翻译： 在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。 提出了减少这些电流的技术。 在第一方面，减少了在字线上同时编程的单元的数量。 在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。 多个单元可以并行编程，但是它们被布置成处于分开的平面中。 这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合 这些。 在第二个互补方面，位线上的电压电平改变的速率是可调节的。 通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。 这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

公开(公告)号：US06894343B2

公开(公告)日：2005-05-17

申请号：US09860704

申请日：2001-05-18

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion being positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also described.

摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，所述两个沟槽侧壁为相邻电池提供选择晶体管沟道，以及位于沟槽底部的公共源/漏扩散。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 还描述了用于制造这种快闪EEPROM分离通道单元阵列的技术。

公开(公告)号：US06888752B2

公开(公告)日：2005-05-03

申请号：US10613098

申请日：2003-07-01

申请人： John S. Mangan ,  Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

发明人： John S. Mangan ,  Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

IPC分类号： G11C16/02 ,  G11C16/12 ,  G11C16/04

CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

公开(公告)号：US06717851B2

公开(公告)日：2004-04-06

申请号：US09759835

申请日：2001-01-10

申请人： John S. Mangan ,  Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

发明人： John S. Mangan ,  Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

IPC分类号： G11C1604

CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

摘要翻译： 在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。 提出了减少这些电流的技术。 在第一方面，减少了在字线上同时编程的单元的数量。 在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。 多个单元可以并行编程，但是它们被布置成处于分开的平面中。 这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合 这些。 在第二个互补方面，位线上的电压电平改变的速率是可调节的。 通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。 这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

公开(公告)号：US5659550A

公开(公告)日：1997-08-19

申请号：US494090

申请日：1995-06-23

申请人： Sanjay Mehrotra ,  Winston Lee ,  George Samachisa ,  Stephen J. Gross

发明人： Sanjay Mehrotra ,  Winston Lee ,  George Samachisa ,  Stephen J. Gross

IPC分类号： G01R31/28 ,  G06F11/10 ,  G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50 ,  G06F11/00

CPC分类号： G11C29/76 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C29/82 ,  G11C29/832 ,  G11C29/88 ,  G06F11/1008 ,  G11C16/04 ,  G11C2029/5006

摘要： A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connected respectively to all the sources and drains of each column of cells. The memory system incorporates a word line current detector and an erase line current detector in addition to the usual bit line current detectors. The leakage current of each of the lines are measured after predetermined memory events such as program or erase operations. When a defective row or column is detected, it is electrically isolated from other columns by programming and is mapped out and replaced. Data recovery schemes include reading a defective column by a switched-memory-source-drain technique.

摘要翻译： 具有EEPROM或闪存EEPROM单元的二维阵列的存储器系统可由行和列寻址。 字线连接到每行的所有单元的控制栅极，擦除线连接到每个单元扇区的所有擦除栅极，并且一对位线分别连接到每个单元的所有源和漏极 细胞柱。 存储器系统除了通常的位线电流检测器之外还包括字线电流检测器和擦除线电流检测器。 在预定的存储器事件例如编程或擦除操作之后测量每条线路的漏电流。 当检测到有缺陷的行或列时，通过编程与其他列电隔离，并进行映射和更换。 数据恢复方案包括通过开关式存储器 - 源极 - 漏极技术读取有缺陷的列。

公开(公告)号：US08351236B2

公开(公告)日：2013-01-08

申请号：US12748260

申请日：2010-03-26

申请人： Tianhong Yan ,  George Samachisa

发明人： Tianhong Yan ,  George Samachisa

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/06035 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/025 ,  G11C16/10 ,  G11C2013/0045 ,  G11C2013/0088 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/78 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

公开(公告)号：US08274130B2

公开(公告)日：2012-09-25

申请号：US12582509

申请日：2009-10-20

申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

IPC分类号： H01L29/861

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

公开(公告)号：US20120147650A1

公开(公告)日：2012-06-14

申请号：US13323780

申请日：2011-12-12

申请人： George Samachisa ,  Johann Alsmeier

发明人： George Samachisa ,  Johann Alsmeier

IPC分类号： G11C5/02 ,  H01L21/8239

CPC分类号： H01L27/11551 ,  G11C5/025 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  H01L21/306 ,  H01L21/76224 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

摘要： A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.

摘要翻译： 形成三维存储器作为形成在位于半导体衬底上方不同距离的多层平面上的存储元件的阵列。 存储元件响应于在其上施加的电压差而可逆地改变电导级。 三维阵列包括通过多层平面的作为局部垂直位线的柱线的二维阵列，每个平面上的字线阵列被用于访问存储器元件。 在具有中间柱选择层的CMOS衬底上形成三维存储器。 柱选择层形成有多个柱选择器件，其是形成在CMOS外部的开关晶体管，用于将所选择的行列切换到衬底上相应的金属线。