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    Circuit module component mounting system and method
    25.
    发明申请
    Circuit module component mounting system and method 审中-公开
    电路模块组件安装系统及方法

    公开(公告)号：US20060118936A1

    公开(公告)日：2006-06-08

    申请号：US11003168

    申请日：2004-12-03

    Applicant: Russell Rapport ,  David Roper

    Inventor： Russell Rapport ,  David Roper

    IPC: H01L23/02

    CPC classification number: H01L25/105 ,  H01L23/4985 ,  H01L25/16 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/147 ,  H05K1/189 ,  H01L2924/00

    Abstract: One or more capacitors are mounted within the lateral extent of a module having one or more integrated circuits. Other components may be similarly mounted. In one embodiment, multiple ICs are stacked and interconnected with flexible circuits to form a high-density module. Surface-mount capacitors may be mounted to the flexible circuits. In other embodiments, capacitors are placed at least partially within cutout spaces formed in the flexible circuits. Preferred embodiments have flex circuits with two conducive layers. Module contacts may be used to connect the module to its operating environment.

    Abstract translation: 一个或多个电容器安装在具有一个或多个集成电路的模块的横向范围内。 其他部件也可以类似地安装。 在一个实施例中，多个IC被堆叠并与柔性电路互连以形成高密度模块。 表面贴装电容器可以安装到柔性电路。 在其他实施例中，电容器至少部分地放置在柔性电路中形成的切割空间内。 优选实施例具有带有两个导通层的柔性电路。 模块触点可用于将模块连接到其操作环境。

    Clock driver with instantaneously selectable phase and method for use in data communication systems
    30.
    发明授权
    Clock driver with instantaneously selectable phase and method for use in data communication systems 有权
    具有瞬时可选相位的时钟驱动器和用于数据通信系统的方法

    公开(公告)号：US06282210B1

    公开(公告)日：2001-08-28

    申请号：US09133297

    申请日：1998-08-12

    Applicant: Russell Rapport ,  Jeff Buchle

    Inventor： Russell Rapport ,  Jeff Buchle

    IPC: H04J306

    CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  H03L7/07 ,  H03L7/0812

    Abstract: A clock driver providing a clock signal, from an input clock signal, that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system. A clock driver of the present invention generates an output clock signal from an input clock signal having a periodic wave form and provides the flexibility for selecting or changing the magnitude of the phase-offset of the output clock signal, in relationship to the input clock signal, for desired clock periods and optionally desired half-clock periods. A method is provided for the self-calibration of critical delay elements. The present invention also includes a method for synchronizing data transfers between a bus master device that is clocked by a system clock and a plurality of synchronous DRAM devices (SDRAM) that are clocked by a local clock; the local clock has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. A Dual In Line Module (DIMM) of the present invention receives a system clock signal and provides a local clock signal to an array of SDRAM devices, wherein the local clock signal has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. Optionally the magnitude of the phase-offset of the local clock signal is selectable through software providing the flexibility to support a method for determining the optional phase-offsets by software using an iterative process involving trial and error.

    Abstract translation: 从具有瞬时可选相位的输入时钟信号提供时钟信号的时钟驱动器以及用于在多信号总线通信系统中同步数据传输的方法。 本发明的时钟驱动器从具有周期波形的输入时钟信号产生输出时钟信号，并提供了与输入时钟信号相关的选择或改变输出时钟信号的相位偏移量的灵活性 ，用于期望的时钟周期和可选的期望的半时钟周期。 提供了一种用于关键延迟元件的自校准的方法。 本发明还包括一种用于在由系统时钟计时的总线主设备和由本地时钟计时的多个同步DRAM设备（SDRAM））之间同步数据传输的方法; 本地时钟具有与系统时钟信号相关的用于读周期的第一相位偏移和用于写周期的第二相位偏移。 本发明的双列直插式模块（DIMM）接收系统时钟信号并向SDRAM器件阵列提供本地时钟信号，其中本地时钟信号与系统时钟信号相关，具有第一相位偏移 用于读周期，第二个相位偏移用于写周期。 可选地，可以通过软件提供本地时钟信号的相位偏移的幅度，该软件提供了灵活性，以支持通过软件使用涉及试错的迭代过程来确定可选相位偏移的方法。

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