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    Efficient generalized tensor product codes encoding schemes
    21.
    发明授权
    Efficient generalized tensor product codes encoding schemes 有权

    公开(公告)号：US10333554B2

    公开(公告)日：2019-06-25

    申请号：US15639475

    申请日：2017-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Moshe Ben Ari ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong ,  Yaron Shany

    IPC: H03M13/00 ,  H03M13/15 ,  H03M13/29

    Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.

    Mapping bits to memory cells using sector spreading
    22.
    发明授权
    Mapping bits to memory cells using sector spreading 有权

    公开(公告)号：US10262728B2

    公开(公告)日：2019-04-16

    申请号：US15288443

    申请日：2016-10-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Iddo Naiss ,  Noam Livne ,  Elona Erez ,  Jun Jin Kong

    IPC: G06F11/10 ,  G11C11/56 ,  G11C29/52 ,  G11C29/00

    Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

    Memory systems having improved out-of-order execution of commands and methods for operating the same
    26.
    发明授权
    Memory systems having improved out-of-order execution of commands and methods for operating the same 有权
    具有改进的命令无序执行的存储器系统及其操作方法

    公开(公告)号：US09477408B1

    公开(公告)日：2016-10-25

    申请号：US14686391

    申请日：2015-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amitai Perlstein ,  Amir Bennatan ,  Hanan Lechtman ,  Jun Jin Kong ,  Michael Erlihson

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

    Abstract: A memory device controller includes a main processor and a sequencer. The sequencer is configured to: estimate a time interval required to complete execution of a set of atom commands allocated to a channel of a non-volatile memory; calculate, for each of the plurality of atom commands, an urgency value associated with completing execution of a corresponding memory command after expiration of the time interval required to complete execution of the set of atom commands allocated to the channel; schedule each of the plurality of atom commands in the set of atom commands for execution by the non-volatile memory based on the calculated urgency values; and output the plurality of atom commands to the non-volatile memory for execution in the scheduled order.

    Abstract translation: 存储器件控制器包括主处理器和定序器。 定序器被配置为：估计完成执行分配给非易失性存储器的通道的一组原子命令所需的时间间隔; 对于所述多个原子命令中的每一个计算与完成执行分配给所述通道的所述原子命令集合所需的时间间隔期满之后完成对应的存储器命令的执行相关联的紧急度值; 基于所计算出的紧急度，安排所述原子命令集中的所述多个原子命令中的每一个，以由所述非易失性存储器执行; 并将多个原子命令输出到非易失性存储器，以按预定顺序执行。

    Method of operating data compression circuit and devices to perform the same
    27.
    发明授权
    Method of operating data compression circuit and devices to perform the same 有权
    操作数据压缩电路的方法和执行相同的设备

    公开(公告)号：US09444490B2

    公开(公告)日：2016-09-13

    申请号：US14146846

    申请日：2014-01-03

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Man Keun Seo ,  Dae Wook Kim ,  Hong Rak Son ,  Jun Jin Kong

    IPC: H03M7/38 ,  H03M7/30 ,  G06F13/14

    CPC classification number: H03M7/30 ,  G06F13/14 ,  G06F13/1668 ,  H03M7/3084 ,  H03M7/3091

    Abstract: A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.

    Abstract translation: 一种操作数据压缩电路的方法包括接收和存储多个数据块，直到高速缓存满了，并且当高速缓存已满时将已经存储在高速缓存中的数据块写入缓冲存储器。 该方法还包括对每个数据块执行强制文字/文字编码，而不管每个数据块在高速缓存满时的重复性。

    Method and apparatus for encoding and decoding data in memory system
    28.
    发明授权
    Method and apparatus for encoding and decoding data in memory system 有权
    用于在存储器系统中对数据进行编码和解码的方法和装置

    公开(公告)号：US09384087B2

    公开(公告)日：2016-07-05

    申请号：US14542828

    申请日：2014-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moshe Twitto ,  Avner Dor ,  Jun Jin Kong ,  Jung Soo Chung

    IPC: H03M13/03 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00

    CPC classification number: G06F11/1012 ,  G06F11/108 ,  G06F2211/109 ,  H03M13/036 ,  H03M13/1157 ,  H03M13/118 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/611

    Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

    Abstract translation: 示例性实施例公开了用于在存储器系统中对数据进行编码和解码的方法和装置。 在根据发明构思的示例性实施例的编码方法中，基于被存储的数据和辅助数据的组合，根据被卡住的小区和基于关于被卡住的小区的坐标的信息的编码矩阵和 卡住细胞。 生成的码字包括对应于与被卡住的小区的坐标对应的地址处的卡住的小区的值的数据。 在根据发明构思的示例性实施例的解码方法中，可以通过将用于编码的编码矩阵的逆矩阵乘以码字来生成数据。

    Non-volatile memory device and programming method using fewer verification voltages than programmable data states
    29.
    发明授权
    Non-volatile memory device and programming method using fewer verification voltages than programmable data states 有权
    非易失性存储器件和使用比可编程数据状态更少的验证电压的编程方法

    公开(公告)号：US09202576B2

    公开(公告)日：2015-12-01

    申请号：US14211077

    申请日：2014-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoav Shereshevski ,  Avner Dor ,  Shmuel Dashevsky ,  Jun Jin Kong ,  Pil Sang Yoon

    IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3459

    Abstract: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.

    Abstract translation: 非易失性存储器件的编程方法包括： 定义一组验证电压，将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压，基于目标验证电压和第一目标计算额外脉冲数 编程电压，通过向存储单元施加增量步进脉冲程序（ISPP）脉冲，然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压 并且当阈值电压被验证为等于或大于目标验证电压时，进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。

    SOFT AND HARD DECISION MESSAGE-PASSING DECODING
    30.
    发明申请
    SOFT AND HARD DECISION MESSAGE-PASSING DECODING 有权
    软和硬决策消息传递解码

    公开(公告)号：US20150263760A1

    公开(公告)日：2015-09-17

    申请号：US14215659

    申请日：2014-03-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： ERAN HOF ,  Jun Jin Kong

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1108 ,  H03M13/1111 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/2957 ,  H03M13/3707

    Abstract: A decoder unit is configured to perform a decoding on encoded data. The decoder unit includes a data bus comprising a number N of data lines, a local memory configured to store messages for a message-passing decoding and communicate the messages across the data bus, a plurality of first decoder processing units, wherein each first decoder processing unit is configured to perform the message-passing decoding by communicating with the local memory using a number A of the data channels, and a plurality of second decoder processing units, where each second decoder processing unit is configured to perform the message-passing decoding by communicating with the local memory using a number B of the data lines. N is at least two, A and B are less than or equal to N, and A is different from B.

    Abstract translation: 解码器单元被配置为对编码数据执行解码。 解码器单元包括数据总线，数据总线包括N个数据线，本地存储器被配置为存储用于消息传递解码的消息，并且跨数据总线传送消息;多个第一解码器处理单元，其中每个第一解码器处理 单元被配置为通过使用数字信道的数量A与本地存储器通信来执行消息传递解码，以及多个第二解码器处理单元，其中每个第二解码器处理单元被配置为通过以下方式执行消息传递解码： 使用B数据线与本地存储器进行通信。 N至少为2，A和B小于或等于N，A与B不同。

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