公开(公告)号：US11963343B2

公开(公告)日：2024-04-16

申请号：US17892190

申请日：2022-08-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi Kunitake ,  Ryunosuke Honda ,  Tomoaki Atsumi

IPC: G11C11/4074 ,  G11C11/405 ,  H01L29/66 ,  H10B12/00

CPC classification number: H10B12/00 ,  G11C11/405 ,  G11C11/4074 ,  H01L29/66083

Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.

公开(公告)号：US11848697B2

公开(公告)日：2023-12-19

申请号：US17616539

申请日：2020-06-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki Ikeda ,  Hitoshi Kunitake

IPC: H03K17/16 ,  H03K17/693 ,  H04B1/44

CPC classification number: H04B1/44 ,  H03K17/16 ,  H03K17/693

Abstract: A communication device capable of transmitting and receiving high-potential signals is provided. The communication device includes a duplexer including first to fourth transistors, a transmission terminal, a reception terminal, an antenna terminal, and first and second control terminals. The transmission terminal is electrically connected to one of a source and a drain of each of the first and second transistors. The reception terminal is electrically connected to one of a source and a drain of each of the third and fourth transistors. The antenna terminal is electrically connected to the other of the source and the drain of each of the second and fourth transistors. The first control terminal is electrically connected to gates of the second and third transistors. The second control terminal is electrically connected to gates of the first and fourth transistors. A semiconductor of each of the first to fourth transistors contains a metal oxide.

公开(公告)号：US11823733B2

公开(公告)日：2023-11-21

申请号：US17600379

申请日：2020-04-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi Kunitake ,  Yuto Yakubo ,  Takanori Matsuzaki ,  Yuki Okamoto ,  Tatsuya Onuki

IPC: G11C5/06 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C11/4085 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/789

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

公开(公告)号：US11043186B2

公开(公告)日：2021-06-22

申请号：US15792235

申请日：2017-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Yoshiyuki Kurokawa

IPC: G09G5/10 ,  H04L27/18 ,  H04L27/32 ,  H04L5/06 ,  H04L27/02 ,  H04L27/26 ,  G02F1/1335 ,  G02F1/13357 ,  G02F1/1343 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786

Abstract: A method for transmitting image data to a display device at high speed is provided. Image data to be transmitted is input to a phase modulation portion, and is mixed with a high-frequency carrier wave. The carrier wave is modulated with a technique of phase-shift keying, and output to a transmission line determined in consideration of the transmission characteristics of the high-frequency wave. A phase regulating portion of the phase modulation portion has a function of adjusting the amount of change in phase with the use of an electric signal. A phase demodulation portion beyond the transmission line demodulates the modulated carrier wave and extracts the image data. The multi-bit image data can be transmitted by the technique of the phase-shift keying. The high-speed transmission enables serial conversion of the original image data and decreases the number of transmission lines.

公开(公告)号：US12207462B2

公开(公告)日：2025-01-21

申请号：US17776342

申请日：2020-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki Tsuda ,  Hiromichi Godo ,  Satoru Ohshita ,  Hitoshi Kunitake

IPC: H10B41/35 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

公开(公告)号：US12193236B2

公开(公告)日：2025-01-07

申请号：US17772280

申请日：2020-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Satoru Ohshita ,  Kazuki Tsuda ,  Tatsuya Onuki

IPC: H10B43/40 ,  G11C16/08 ,  H10B43/27

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

公开(公告)号：US12156410B2

公开(公告)日：2024-11-26

申请号：US17629804

申请日：2020-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Tatsuya Onuki ,  Yuki Okamoto ,  Hideki Uochi ,  Satoru Okamoto ,  Hiromichi Godo ,  Kazuki Tsuda ,  Hitoshi Kunitake

IPC: H10B63/00 ,  H10B41/27 ,  H10B43/27

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US12132057B2

公开(公告)日：2024-10-29

申请号：US17639744

申请日：2020-08-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Tatsuya Onuki ,  Hajime Kimura ,  Takayuki Ikeda ,  Shunpei Yamazaki

IPC: H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L27/1255 ,  H01L27/1225 ,  H01L29/78648 ,  H01L29/7869 ,  H10B12/00

Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.

公开(公告)号：US12095440B2

公开(公告)日：2024-09-17

申请号：US17765046

申请日：2020-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki Ohshima ,  Hitoshi Kunitake ,  Yuto Yakubo ,  Takayuki Ikeda

IPC: H03H7/38 ,  H01L21/02 ,  H01L21/822 ,  H01L27/088 ,  H03F3/19 ,  H03F3/60

CPC classification number: H03H7/38 ,  H01L21/02565 ,  H01L21/822 ,  H01L27/088 ,  H03F3/19 ,  H03F3/60

Abstract: An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.

公开(公告)号：US11935961B2

公开(公告)日：2024-03-19

申请号：US17284553

申请日：2019-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Eri Sato ,  Tatsuya Onuki ,  Yuto Yakubo ,  Hitoshi Kunitake

IPC: H03F3/45 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678

Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.