公开(公告)号：US20170207347A1

公开(公告)日：2017-07-20

申请号：US15408719

申请日：2017-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/146 ,  H01L29/49 ,  H01L27/12 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20160247832A1

公开(公告)日：2016-08-25

申请号：US15041502

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Yuta ENDO ,  Kazuya HANAOKA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/475 ,  H01L21/47573 ,  H01L27/1207 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

Abstract translation: 提供具有降低的寄生电容的半导体器件。 半导体器件包括第一绝缘层; 第一绝缘层上的第一氧化物层; 在所述第一氧化物层上的半导体层; 半导体层上的源电极层和漏电极层; 在所述第一绝缘层上的第二绝缘层; 在第二绝缘层上的第三绝缘层，源电极层和漏电极层; 半导体层上的第二氧化物层; 第二氧化物层上的栅极绝缘层; 栅绝缘层上的栅电极层; 以及第三绝缘层，第二氧化物层，栅极绝缘层和栅极电极层上的第四绝缘层。

公开(公告)号：US20160190347A1

公开(公告)日：2016-06-30

申请号：US15062268

申请日：2016-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Kazuya HANAOKA ,  Yoshiyuki KOBAYASHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

公开(公告)号：US20150221754A1

公开(公告)日：2015-08-06

申请号：US14688199

申请日：2015-04-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Suguru HONDO ,  Akihisa SHIMOMURA ,  Masaki KOYAMA ,  Motomu KURATA ,  Kazuya HANAOKA ,  Sho NAGAMATSU ,  Kosei NEI ,  Toru HASEGAWA

IPC: H01L29/66 ,  H01L21/46

CPC classification number: H01L29/66969 ,  H01L21/46 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.

Abstract translation: 提供具有稳定电特性的包括氧化物半导体膜的晶体管。 还提供了具有优异的导通状态特性的包括氧化物半导体膜的晶体管。 其中形成具有低电阻的氧化物半导体膜并且氧化物半导体膜的沟道区的电阻增加的半导体器件。 注意，氧化物半导体膜经受用于降低电阻以降低电阻的工艺。 用于降低氧化物半导体膜的电阻的方法可以是例如在高于或等于450℃且低于或等于740℃的温度下的激光处理或热处理。 例如，可以通过等离子体氧化或氧离子的注入来提高具有低电阻的氧化物半导体膜的沟道区域的电阻的方法。

公开(公告)号：US20150187917A1

公开(公告)日：2015-07-02

申请号：US14656125

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki TEZUKA ,  Atsuo ISOBE ,  Takehisa HATANO ,  Kazuya HANAOKA

IPC: H01L29/66 ,  H01L21/463 ,  H01L21/465

CPC classification number: H01L29/66969 ,  H01L21/463 ,  H01L21/465 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/7869

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

Abstract translation: 提供具有高电特性的小型化晶体管。 形成作为源电极层和漏电极层的导电膜以覆盖氧化物半导体层和沟道保护层，然后形成与氧化物半导体层和沟道保护层重叠的导电膜的区域， 通过化学机械抛光处理除去。 在除去作为源极电极层和漏极电极层的导电膜的一部分的工序中，不进行使用抗蚀剂掩模的蚀刻工序，所以可以精确地进行精加工。 通过沟道保护层，可以抑制由于在导电膜上的化学机械抛光处理对氧化物半导体层的损坏或膜厚度的降低。

公开(公告)号：US20140349444A1

公开(公告)日：2014-11-27

申请号：US14454071

申请日：2014-08-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Sho NAGAMATSU

IPC: H01L29/66 ,  H01L21/465 ,  H01L21/463 ,  H01L21/02 ,  H01L21/44

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/463 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/04 ,  H01L29/78 ,  H01L29/7869

Abstract: A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

Abstract translation: 一分钟晶体管和微晶体管的制造方法。 源极电极层和漏极电极层各自形成在形成在覆盖半导体层的绝缘层中的对应的开口中。 源电极层的开口和漏电极层的开口分开形成两个不同的步骤。 源极电极层和漏电极层通过在绝缘层上和开口中沉积导电层而形成，然后通过抛光去除位于绝缘层之上的部分。 该制造方法允许稍后的源极电极和漏极电极层彼此靠近并且靠近半导体层的沟道形成区域。 这种结构导致即使在微小结构的情况下也具有高电特性和高制造成品率的晶体管。

公开(公告)号：US20140127868A1

公开(公告)日：2014-05-08

申请号：US14151036

申请日：2014-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

公开(公告)号：US20130161621A1

公开(公告)日：2013-06-27

申请号：US13716899

申请日：2012-12-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Yutaka OKAZAKI ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。