公开(公告)号：US20150171195A1

公开(公告)日：2015-06-18

申请号：US14576400

申请日：2014-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L21/02 ,  H01L29/786 ,  H01L29/04

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/477 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

Abstract translation: 公开了一种具有包括氧化物半导体膜的晶体管的半导体器件。 在半导体装置中，沿着形成在绝缘层中的沟槽设置氧化物半导体膜。 沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分和上端拐角部分，并且氧化物半导体膜设置成与 底面，下端角部，上端角部和沟槽的内壁面。 氧化物半导体膜包括至少在上端角部上方具有基本上垂直于表面的c轴的晶体。

公开(公告)号：US20150060848A1

公开(公告)日：2015-03-05

申请号：US14476921

申请日：2014-09-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Katsuaki TOCHIBAYASHI

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/4757 ,  H01L21/02 ,  H01L21/467 ,  H01L21/469 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/44 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/47573 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode layer positioned over the first electrode layer and including a stacked-layer structure of a first conductive layer and a second conductive layer; and an oxide semiconductor film and an insulating film positioned between the first electrode layer and the second electrode layer in a thickness direction. The first conductive layer and the insulating film have a first opening portion in a region overlapping with the first electrode layer. The oxide semiconductor film has a second opening portion in a region overlapping with the first opening portion. The second conductive layer is in contact with the first electrode layer exposed in the first opening portion and the second opening portion.

Abstract translation: 提供使用氧化物半导体的高度可靠的半导体器件。 半导体器件包括第一电极层; 位于所述第一电极层上并包括第一导电层和第二导电层的层叠结构的第二电极层; 以及在厚度方向上位于第一电极层和第二电极层之间的氧化物半导体膜和绝缘膜。 第一导电层和绝缘膜在与第一电极层重叠的区域中具有第一开口部。 氧化物半导体膜在与第一开口部重叠的区域中具有第二开口部。 第二导电层与暴露在第一开口部分和第二开口部分中的第一电极层接触。

公开(公告)号：US20140339552A1

公开(公告)日：2014-11-20

申请号：US14448024

申请日：2014-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Hideaki KUWABARA ,  Mari TERASHIMA

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface. Further, a gate electrode layer is formed over the oxide semiconductor layer with a gate insulating layer interposed therebetween and impurities are introduced with the gate electrode layer used as a mask. Then, a conductive layer is provided on a side surface of the gate electrode layer in the channel length direction, whereby an Lov region is formed while maintaining a scaled-down channel length and entry of light from above into the oxide semiconductor layer is prevented.

Abstract translation: 提供包括使用氧化物半导体的晶体管的高度可靠的半导体器件。 在形成源电极层和漏电极层之后，在这些电极层之间的间隙中形成岛状氧化物半导体层，使得氧化物半导体层的侧表面被布线覆盖，从而防止光 通过侧面进入氧化物半导体层。 此外，在氧化物半导体层上形成栅极电极层，其间插入有栅极绝缘层，并且将杂质与用作掩模的栅极电极层一起引入。 然后，在栅极电极层的沟道长度方向的侧面上设置导电层，由此形成Lov区，同时保持按比例缩小的沟道长度，防止从上方入射到氧化物半导体层中的光。

公开(公告)号：US20140326992A1

公开(公告)日：2014-11-06

申请号：US14258528

申请日：2014-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Suguru HONDO ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Naoto KUSUMOTO

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.

Abstract translation: 提供了可以在简单的工艺中小型化并且可以防止由于小型化导致的电特性劣化的半导体器件。 半导体器件包括氧化物半导体层，与氧化物半导体层接触的第一导体和与第一导体接触的绝缘体。 此外，在氧化物半导体层，第一导体和绝缘体中设置有开口部。 在开口部分中，氧化物半导体层，第一导体和绝缘体的侧表面被对准，并且氧化物半导体层和第一导体通过侧面接触电连接到第二导体。

公开(公告)号：US20140103340A1

公开(公告)日：2014-04-17

申请号：US14054130

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L29/045 ,  H01L29/26 ,  H01L29/78 ,  H01L29/7869

Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed.

Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层，漏电极层和栅电极层的金属膜，由此抑制氧向金属膜的扩散。

公开(公告)号：US20140103338A1

公开(公告)日：2014-04-17

申请号：US14054082

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L21/02 ,  H01L29/26 ,  H01L29/78

CPC classification number: H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/26 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for a metal film of a source electrode layer and a drain electrode layer, whereby diffusion of oxygen to the metal film is suppressed.

Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层和漏电极层的金属膜，从而抑制氧向金属膜的扩散。

公开(公告)号：US20130280867A1

公开(公告)日：2013-10-24

申请号：US13924741

申请日：2013-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66

CPC classification number: H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

公开(公告)号：US20130119376A1

公开(公告)日：2013-05-16

申请号：US13666153

申请日：2012-11-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Hideaki KUWABARA ,  Mari TERASHIMA

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface. Further, a gate electrode layer is formed over the oxide semiconductor layer with a gate insulating layer interposed therebetween and impurities are introduced with the gate electrode layer used as a mask. Then, a conductive layer is provided on a side surface of the gate electrode layer in the channel length direction, whereby an Lov region is formed while maintaining a scaled-down channel length and entry of light from above into the oxide semiconductor layer is prevented.

Abstract translation: 提供包括使用氧化物半导体的晶体管的高度可靠的半导体器件。 在形成源电极层和漏电极层之后，在这些电极层之间的间隙中形成岛状氧化物半导体层，使得氧化物半导体层的侧表面被布线覆盖，从而防止光 通过侧面进入氧化物半导体层。 此外，在氧化物半导体层上形成栅极电极层，其间插入有栅极绝缘层，并且将杂质与用作掩模的栅极电极层一起引入。 然后，在栅极电极层的沟道长度方向的侧面上设置导电层，由此形成Lov区，同时保持按比例缩小的沟道长度，并且防止从上方进入到氧化物半导体层的光。

公开(公告)号：US20130095587A1

公开(公告)日：2013-04-18

申请号：US13692310

申请日：2012-12-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L33/00 ,  H01L29/66

CPC classification number: H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract translation: 本发明提供了一种制造具有少量漏电流的高可靠性半导体器件的方法。 在制造薄膜晶体管的方法中，使用抗蚀剂掩模进行蚀刻以在薄膜晶体管中形成背沟道部分，去除抗蚀剂掩模，蚀刻一部分后沟道以除去蚀刻残留物等 留在后通道部分，由此可以减少由残渣等引起的泄漏电流。 背沟道部分的蚀刻步骤可以通过使用非偏压的干蚀刻来进行。

公开(公告)号：US20250081537A1

公开(公告)日：2025-03-06

申请号：US18950834

申请日：2024-11-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Katsuaki TOCHIBAYASHI ,  Tsutomu MURAKAWA ,  Erika TAKAHASHI

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/66 ,  H10B12/00

Abstract: A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.