公开(公告)号：US20140339541A1

公开(公告)日：2014-11-20

申请号：US14272853

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: H01L27/115 ,  H01L27/108

CPC classification number: H01L27/11563 ,  G11C11/005 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

Abstract translation: 具有新型结构的半导体器件，其中提供了即使使用小型化元件来保持数据所需的存储容量。 在半导体器件中，电容器的电极是设置在与晶体管的栅极相同的层中的电极和设置在与晶体管的源极和漏极相同的层中的电极。 此外，在不同的层中设置提供晶体管的栅极的层和连接多个存储器中的晶体管的栅极的布线层。 利用这种结构，可以减小在晶体管的栅极周围形成的寄生电容，并且可以在更大的面积中形成电容器。

公开(公告)号：US12289878B2

公开(公告)日：2025-04-29

申请号：US17623299

申请日：2020-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Shunpei Yamazaki

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00 ,  H01L21/8258 ,  H01L27/06

Abstract: A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

公开(公告)号：US12230358B2

公开(公告)日：2025-02-18

申请号：US18043103

申请日：2021-08-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC: G11C11/40 ,  G11C7/10 ,  G11C11/4096

Abstract: A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.

公开(公告)号：US12211584B2

公开(公告)日：2025-01-28

申请号：US17802281

申请日：2021-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Tatsuya Onuki ,  Munehiro Kozuma ,  Takanori Matsuzaki

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

公开(公告)号：US12156396B2

公开(公告)日：2024-11-26

申请号：US17424664

申请日：2019-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Tatsuya Onuki ,  Takahiko Ishizu ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H10B12/00 ,  G11C5/02 ,  H01L27/12 ,  H01L29/786 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

公开(公告)号：US12063798B2

公开(公告)日：2024-08-13

申请号：US18203736

申请日：2023-05-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC: H01L27/12 ,  H01L29/786 ,  H10B99/00

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

公开(公告)号：US11876138B2

公开(公告)日：2024-01-16

申请号：US17284553

申请日：2019-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Eri Sato ,  Tatsuya Onuki ,  Yuto Yakubo ,  Hitoshi Kunitake

IPC: H03F3/45 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678

Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

公开(公告)号：US11854599B2

公开(公告)日：2023-12-26

申请号：US17977099

申请日：2022-10-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko Ishizu ,  Yuto Yakubo ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC: G11C11/40 ,  G11C11/4074 ,  G11C11/4096 ,  H01L29/786 ,  H01L27/12 ,  H10B99/00

CPC classification number: G11C11/4074 ,  G11C11/4096 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H10B99/00

Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.

公开(公告)号：US11696455B2

公开(公告)日：2023-07-04

申请号：US17509157

申请日：2021-10-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  H10B99/00

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

公开(公告)号：US11657867B2

公开(公告)日：2023-05-23

申请号：US17377757

申请日：2021-07-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C11/40 ,  G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  H01L27/108

CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10805

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.