公开(公告)号：US20230018223A1

公开(公告)日：2023-01-19

申请号：US17847241

申请日：2022-06-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shoki MIYATA ,  Yuto YAKUBO ,  Yoshiyuki KUROKAWA

IPC: H03K19/096 ,  H03M1/46 ,  H03K19/20

Abstract: A semiconductor device with reduced power consumption can be provided. The semiconductor device includes a first transistor and a second transistor. The first transistor is a p-channel transistor including silicon in a channel formation region and the second transistor is an n-channel transistor including a metal oxide in a channel formation region. The metal oxide includes indium, an element M (e.g., gallium), and zinc. A gate of the first transistor is electrically connected to a gate of the second transistor, and one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The first transistor and the second transistor can each operate in a subthreshold region.

公开(公告)号：US20220254402A1

公开(公告)日：2022-08-11

申请号：US17625922

申请日：2020-07-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto YAKUBO ,  Takahiko ISHIZU

IPC: G11C11/405 ,  G11C11/4096 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.

公开(公告)号：US20220208248A1

公开(公告)日：2022-06-30

申请号：US17600379

申请日：2020-04-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Yuto YAKUBO ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Tatsuya ONUKI

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/00

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

公开(公告)号：US20170062482A1

公开(公告)日：2017-03-02

申请号：US15245310

申请日：2016-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/544 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

Abstract translation: 提供在其制造过程中不容易被ESD损坏的半导体器件。 带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层被提供以与切割线重叠。 在诸如晶体管的半导体器件周围设置一个其带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层。 该层可以处于浮置状态或者可以被提供特定的电位。

公开(公告)号：US20250141355A1

公开(公告)日：2025-05-01

申请号：US18986896

申请日：2024-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Kousuke SASAKI ,  Yuto YAKUBO ,  Kei TAKAHASHI

IPC: H02M3/156 ,  H02H7/18 ,  H10D30/67 ,  H10D86/40 ,  H10D86/60

Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.

公开(公告)号：US20250040116A1

公开(公告)日：2025-01-30

申请号：US18780752

申请日：2024-07-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takanori MATSUZAKI ,  Yuto YAKUBO ,  Yuki OKAMOTO ,  Hideki UOCHI

IPC: H10B12/00

Abstract: A novel memory device is provided. A plurality of memory cells each including two vertical transistors are connected in series. One of the two transistors functions as a transistor for writing data, and the other functions as a transistor for reading the data that has been written to the memory cell. Data written to the memory cell is retained in a gate of the reading transistor. A transistor with low off-state current is used as the writing transistor.

公开(公告)号：US20230188094A1

公开(公告)日：2023-06-15

申请号：US17923653

申请日：2021-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Shoki MIYATA ,  Akio SUZUKI ,  Takayuki IKEDA

IPC: H03D7/14

CPC classification number: H03D7/1458 ,  H01L29/78648

Abstract: A novel semiconductor device is provided. The semiconductor device includes a mixer circuit and a bias circuit. The mixer circuit includes a voltage-to-current conversion portion, a current switch portion, and a current-to-voltage conversion portion. The bias circuit includes a bias supply portion and a first transistor. The voltage-to-current conversion portion includes a second transistor and a third transistor. The bias supply portion has a function of outputting a bias voltage to be supplied to a gate of the second transistor and a gate of the third transistor. One of a source and a drain of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor. The first transistor is turned off when the bias voltage is supplied, and the first transistor is turned on when the supply of the bias voltage is stopped.

公开(公告)号：US20230130800A1

公开(公告)日：2023-04-27

申请号：US17914498

申请日：2021-03-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yuto YAKUBO ,  Takayuki IKEDA ,  Shoki MIYATA ,  Hiroshi KADOMA ,  Kaori OGITA

IPC: H01M10/615 ,  H01M10/0525 ,  H01M10/48 ,  H01M10/63 ,  H01M10/625

Abstract: A control system for a secondary battery which is less affected by the ambient temperature by performing temperature control of the secondary battery is provided. A control system for a secondary battery which is less affected by the ambient temperature and in which a plurality of kinds of secondary batteries are used for temperature control is achieved and mounted on a vehicle. Specifically, when the ambient temperature is low, some of second secondary batteries are heated by self-heating of a first secondary battery. After the second secondary batteries are sufficiently heated, the rest of the second secondary batteries are heated in stages by self-heating of the some of the second secondary batteries whose temperature has been increased. Whether the some or all of the second secondary batteries are sufficiently heated can be confirmed if the temperatures of a plurality of temperature sensors provided in the second secondary batteries are within the operating temperature range of the second secondary batteries. For example, with the use of a temperature sensing terminal (T terminal) for a temperature sensor, a switch is closed when the internal temperature of the secondary batteries is out of the operating temperature range.

公开(公告)号：US20230110439A1

公开(公告)日：2023-04-13

申请号：US17977099

申请日：2022-10-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko ISHIZU ,  Yuto YAKUBO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C11/4074 ,  G11C11/4096

Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.

公开(公告)号：US20220271669A1

公开(公告)日：2022-08-25

申请号：US17612387

申请日：2020-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Hitoshi KUNITAKE ,  Takayuki IKEDA

IPC: H02M3/158 ,  H02M1/34 ,  H01L29/786

Abstract: A semiconductor device in which an increase in circuit area is inhibited is provided. The semiconductor device includes a first circuit layer and a second circuit layer over the first circuit layer; the first circuit layer includes a first transistor; the second circuit layer includes a second transistor; a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor; a source and a drain of the second transistor are electrically connected to the other of the source and the drain of the first transistor; and a semiconductor layer of the second transistor contains a metal oxide.