公开(公告)号：US10429581B1

公开(公告)日：2019-10-01

申请号：US16189125

申请日：2018-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abu Thomas ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/126 ,  G02B6/13 ,  G02B6/293

Abstract: Structures for a polarization splitter and methods of forming a polarization splitter. A multi-mode interference region includes a first waveguide and a second waveguide arranged in a stack over the first waveguide. First and second input ports are connected with the multi-mode interference region. First and second output ports are connected with the multi-mode interference region.

公开(公告)号：US09799767B2

公开(公告)日：2017-10-24

申请号：US14940597

申请日：2015-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/7781

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.

公开(公告)号：US09716174B2

公开(公告)日：2017-07-25

申请号：US13945455

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795

Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.

公开(公告)号：US20170141227A1

公开(公告)日：2017-05-18

申请号：US14940655

申请日：2015-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/7781

Abstract: One method disclosed includes forming first, second and third fins for a first NMOS device, a PMOS device and a second NMOS device, respectively. According to this method, the first fin consists entirely of the substrate material, the second and third fins comprise a lower substrate fin portion made of the substrate material and an upper fin portion made of a second semiconductor material and a third semiconductor material, respectively, wherein the second semiconductor material and the third semiconductor material are each different from the substrate material. The method also includes forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device.

公开(公告)号：US09589849B2

公开(公告)日：2017-03-07

申请号：US14633353

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/762 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract translation: 本文公开的一种说明性方法包括形成多个初始翅片，其具有与基底相同的初始轴向长度和相同的初始应变，执行至少一个蚀刻工艺以将第一翅片切割成第一轴向 并且将第二翅片切割成小于第一轴向长度的第二轴向长度，其中切割的第一翅片保持初始应变的第一量，并且切割的第二翅片保持初始应变的约零或第二量 的初始应变小于第一量，并且围绕第一和第二切割翅片形成栅极结构以形成FinFET器件。

公开(公告)号：US09508853B2

公开(公告)日：2016-11-29

申请号：US15073936

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201 ,  H01L21/306 ,  H01L29/10 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括围绕初始鳍片的一部分形成牺牲栅极结构，在牺牲栅极结构的相对侧上形成侧壁间隔物，并去除牺牲栅极 结构，从而限定替换栅极腔，通过替代栅极腔执行蚀刻工艺以去除初始翅片的部分，从而限定在侧壁间隔物下方的减小尺寸的翅片和凹陷，形成至少一个替代外延半导体 在更换的浇口腔体和侧壁间隙的凹槽内围绕减小尺寸的翅片的覆层材料，以及在至少一个替代的外延半导体包层材料周围的置换栅极腔内形成替换栅极结构。

公开(公告)号：US09496354B2

公开(公告)日：2016-11-15

申请号：US14812150

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/285 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US09431306B2

公开(公告)日：2016-08-30

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/02 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域。

公开(公告)号：US20160225659A1

公开(公告)日：2016-08-04

申请号：US14608729

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76213 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片，所述翅片具有包含氧化阻滞注入区域的下部第一部分和基本上不含氧化延迟注入区域的上部第二部分 在翅片的上部的相对侧上形成侧壁间隔物，形成邻近侧壁间隔物和鳍片下部的上部第二部分的第一绝缘材料层，并且第一绝缘材料层 位置，进行热退火处理以将与第一绝缘材料层接触的翅片的上部第二部分的部分转换成位于翅片的下部第一部分下方的翅片下方的氧化物翅片隔离区域。

公开(公告)号：US09373721B2

公开(公告)日：2016-06-21

申请号：US14175113

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Michael Hargrove

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L27/088 ,  H01L27/12 ,  H01L29/10 ,  H01L29/778

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/778

Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Abstract translation: 所公开的一种装置包括围绕翅片的周边表面定位的栅极结构，沟道半导体材料层，其在器件的沟道长度方向上具有轴向长度，其大致对应于位于栅极之间的栅极结构的总宽度 结构并且围绕翅片的外周表面周围，其中沟道半导体材料层的内表面与翅片的外周表面间隔开并且不接触鳍的外周表面。 公开的一种方法尤其涉及在翅片周围形成第一和第二层半导体材料，围绕第二半导体材料形成栅极结构，去除位于侧壁间隔横向外侧的第一和第二半导体层的部分，以及 去除位于第二半导体材料层下方的第一半导体材料层。