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公开(公告)号：US10255973B2
公开(公告)日：2019-04-09
申请号：US15797732
申请日：2017-10-30
摘要： An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
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公开(公告)号：US10115470B2
公开(公告)日：2018-10-30
申请号：US15804790
申请日：2017-11-06
IPC分类号： G11C16/28 , G11C16/08 , G05F3/24 , G11C5/14 , G11C16/30 , G11C7/14 , G11C16/10 , G11C16/14 , G11C16/24 , G11C7/12 , G11C7/04 , G11C8/10
摘要： A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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23.发明申请公开(公告)号：US20180122470A1
公开(公告)日：2018-05-03
申请号：US15598962
申请日：2017-05-18
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2213/79 , G11C2213/82
摘要： A non-volatile memory includes a number of bit lines, a number of source lines, and a number of memory cells of a non-volatile type. Each memory cell is coupled between a respective bit line and a respective source line. One or more discharge lines are coupled to a reference-voltage terminal. A number of controlled switches are coupled between a respective source line and a respective discharge line, which can be selectively driven for connecting the respective source line to the respective discharge line so as to form a conductive path between the respective source line and the reference-voltage terminal.
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公开(公告)号：US11355191B2
公开(公告)日：2022-06-07
申请号：US17072887
申请日：2020-10-16
摘要： An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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公开(公告)号：US11107525B2
公开(公告)日：2021-08-31
申请号：US16924760
申请日：2020-07-09
摘要： A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.
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公开(公告)号：US20190317902A1
公开(公告)日：2019-10-17
申请号：US16455155
申请日：2019-06-27
摘要： A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.
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27.发明申请公开(公告)号：US20190214079A1
公开(公告)日：2019-07-11
申请号：US16227438
申请日：2018-12-20
摘要： A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
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公开(公告)号：US20190043574A1
公开(公告)日：2019-02-07
申请号：US16155659
申请日：2018-10-09
摘要： A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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公开(公告)号：US20180285284A1
公开(公告)日：2018-10-04
申请号：US15797940
申请日：2017-10-30
CPC分类号： G06F12/1425 , G06F12/0246 , G06F13/1663 , G06F2212/1052 , G06F2212/7207
摘要： A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.
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公开(公告)号：US20180061499A1
公开(公告)日：2018-03-01
申请号：US15804790
申请日：2017-11-06
IPC分类号： G11C16/28 , G11C5/14 , G11C16/24 , G11C16/14 , G11C16/10 , G11C16/30 , G05F3/24 , G11C7/14 , G11C7/12 , G11C16/08 , G11C7/04 , G11C8/10
CPC分类号： G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
摘要： A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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