公开(公告)号：US20150050597A1

公开(公告)日：2015-02-19

申请号：US14525688

申请日：2014-10-28

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Byung Du Ahn ,  Seung Ho Yeon ,  Sei-Yong Park ,  Mi-Hyae Park ,  Bu Sop Song ,  Tae Gweon Lee ,  Jun Hyun Park ,  Je Hun Lee ,  Jae Woo Park

IPC分类号： G03F7/075 ,  G03F7/20 ,  H01L27/12 ,  G03F7/16

CPC分类号： G03F7/0757 ,  C08G77/16 ,  C08G77/20 ,  C08G77/80 ,  C08L83/04 ,  G02F1/136227 ,  G03F7/16 ,  G03F7/20 ,  H01L23/296 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3258 ,  H01L29/517 ,  H01L2924/0002 ,  C08L83/00 ,  H01L2924/00

摘要： A passivation layer solution composition is provided A passivation layer solution composition according to an exemplary embodiment of the present invention includes an organic siloxane resin represented by Chemical Formula 1 below. In Chemical Formula 1, R is at least one substituent selected from a saturated hydrocarbon or an unsaturated hydrocarbon having from 1 to about 25 carbon atoms, and x and y may each independently be from 1 to about 200, and wherein each wavy line indicates a bond to an H atom or to an x siloxane unit or a y siloxane unit, or a bond to an x siloxane unit or a y siloxane unit of another siloxane chain comprising x siloxane units or y siloxane units or a combination thereof.

摘要翻译： 提供钝化层溶液组合物根据本发明示例性实施方案的钝化层溶液组合物包括由下述化学式1表示的有机硅氧烷树脂。 在化学式1中，R是选自饱和烃或具有1至约25个碳原子的不饱和烃中的至少一个取代基，x和y各自独立地为1至约200，并且其中每个波浪线表示 键合到H原子或x硅氧烷单元或硅氧烷单元，或与包含x硅氧烷单元或y硅氧烷单元或其组合的另一硅氧烷链的x硅氧烷单元或硅氧烷单元的键。

公开(公告)号：US11189680B2

公开(公告)日：2021-11-30

申请号：US16298924

申请日：2019-03-11

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Keon Woo Kim ,  Ji Hyun Ka ,  Tae Hoon Kwon ,  Ho Kyoon Kwon ,  Min Ku Lee ,  Zail Lhee ,  Jin Tae Jeong ,  Seung Ji Cha ,  Byung Du Ahn ,  Jeong Ho Lee

IPC分类号： H01L27/32 ,  H01L51/00 ,  G09G3/3233 ,  H01L27/12

摘要： A display device includes a substrate including a first pixel region, a second pixel region having an area smaller than that of the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a second pixel provided in the second pixel region, a second line connected to the second pixel, an extension line extended to the peripheral region, a dummy part located in the peripheral region to overlap with the extension line, a power line connected to the first and second pixel regions, and a connection line located in the peripheral region to be connected to the dummy part, the connection line being electrically connected to a portion of the second pixel region, wherein the second pixel region includes a first sub-pixel region connected to the connection line and a second sub-pixel region except the first sub-pixel region.

公开(公告)号：US10319745B2

公开(公告)日：2019-06-11

申请号：US14813556

申请日：2015-07-30

申请人： Samsung Display Co., Ltd.

发明人： Dae Young Lee ,  Byung Du Ahn ,  Jung Gun Nam ,  Gug Rae Jo

IPC分类号： H01L27/12 ,  H01L51/52 ,  H01L29/786 ,  H01L29/49

摘要： A display panel comprises a substrate, a gate line, a data line insulated from the gate line, a thin film transistor electrically connected to the gate line and the data line, wherein the thin film transistor comprises a gate electrode group formed on the substrate, a gate insulating film formed on the gate electrode group, an active layer formed on the gate insulating film to at least partially overlap the gate electrode group and a source electrode and a drain electrode formed on the active layer so as to be spaced apart from each other, wherein the gate electrode group includes a first gate electrode formed on the substrate, a second gate electrode formed on the first gate electrode, and an insulating layer between the first gate electrode and the second gate electrode, and wherein the first gate electrode has reflectivity higher than that of the second gate electrode.

公开(公告)号：US10256091B2

公开(公告)日：2019-04-09

申请号：US15290715

申请日：2016-10-11

申请人： Kobe Steel, Ltd. ,  Samsung Display Co., Ltd.

发明人： Hiroaki Tao ,  Aya Miki ,  Shinya Morita ,  Satoshi Yasuno ,  Toshihiro Kugimiya ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L29/786 ,  H01L29/12 ,  H01L29/66 ,  H01L21/477 ,  G02F1/1368

摘要： The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≤0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])>0.5. [In]/([In]+[Zn]+[Sn])≤0.3  (1), [In]/([In]+[Zn]+[Sn])≤1.4×{[Zn]/([Zn]+[Sn])}−0.5  (2), [Zn]/([In]+[Zn]+[Sn])≤0.83  (3), and 0.1≤[In]/([In]+[Zn]+[Sn])  (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

公开(公告)号：US09553201B2

公开(公告)日：2017-01-24

申请号：US14179452

申请日：2014-02-12

申请人： Samsung Display Co., Ltd. ,  Kobe Steel, Ltd.

发明人： Byung Du Ahn ,  Ji Hun Lim ,  Gun Hee Kim ,  Kyoung Won Lee ,  Je Hun Lee ,  Hiroshi Goto ,  Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Yeon Hong Kim ,  Yeon Gon Mo ,  Kwang Suk Kim

IPC分类号： H01L27/14 ,  H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/78696

摘要： The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

摘要翻译： 本发明构思涉及薄膜晶体管和薄膜晶体管阵列面板，并且详细地涉及包括氧化物半导体的薄膜晶体管。 根据本发明构思的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 第一半导体和第二半导体，其与栅电极重叠，栅极绝缘层插入其间，第一半导体和第二半导体彼此接触; 连接到所述第二半导体的源电极; 和连接到第二半导体并面向源电极的漏电极，其中第二半导体包括不包括在第一半导体中的镓（Ga），并且第二半导体中的镓（Ga）的含量大于0 。 ％且小于或等于约33at。 ％。

公开(公告)号：US09508856B2

公开(公告)日：2016-11-29

申请号：US14436241

申请日：2013-10-15

申请人： KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.) ,  Samsung Display Co., Ltd.

发明人： Hiroaki Tao ,  Takeaki Maeda ,  Aya Miki ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  So Young Koo ,  Gun Hee Kim

IPC分类号： H01L29/786

CPC分类号： H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

摘要： Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

摘要翻译： 提供一种薄膜晶体管，其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制，并且实现了稳定的特性。 该薄膜晶体管的特征在于：薄膜晶体管具有由至少含有In，Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。

公开(公告)号：US08969872B2

公开(公告)日：2015-03-03

申请号：US13789335

申请日：2013-03-07

申请人： Samsung Display Co., Ltd.

发明人： Byung Du Ahn ,  Ji Hun Lim ,  Jun Hyung Lim ,  Dae Hwan Kim ,  Jae Hyeong Kim ,  Je Hun Lee ,  Hyun Kwang Jung

IPC分类号： H01L29/04 ,  H01L29/786 ,  H01L21/28

CPC分类号： H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

摘要翻译： 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。