公开(公告)号：US11282995B2

公开(公告)日：2022-03-22

申请号：US16860255

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L33/48 ,  H01L33/56 ,  H01L25/16 ,  H01L25/00 ,  H01L25/075 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L27/15

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

公开(公告)号：US12154988B2

公开(公告)日：2024-11-26

申请号：US17585686

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Jinbum Kim ,  Dahye Kim ,  Ingyu Jang ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

公开(公告)号：US12094974B2

公开(公告)日：2024-09-17

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Dahye Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Dongwoo Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20240170552A1

公开(公告)日：2024-05-23

申请号：US18215254

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbin Chun ,  Jinbum Kim ,  Gyeom Kim ,  Dahye Kim ,  Youngkwang Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including channels spaced apart from each other on a substrate; a gate structure extending on the substrate, the gate structure surrounding lower and upper surfaces and sidewalls of each of the channels; and a source/drain layer on the substrate, the source/drain layer contacting sidewalls of the channels and containing silicon-germanium, the source/drain layer including: a second epitaxial layer having a second germanium concentration; and a first epitaxial layer having a first germanium concentration smaller than the second germanium concentration, the first epitaxial layer covering a lower surface and sidewalls of the second epitaxial layer, wherein the first epitaxial layer includes a protruding portion that protrudes in the first direction and contacts the gate structure, and wherein the protruding portion has a facet that is not curved.

公开(公告)号：US20230317792A1

公开(公告)日：2023-10-05

申请号：US18073806

申请日：2022-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Dahye Kim ,  Kyungbin Chun

IPC: H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes an active region, a plurality of channel layers disposed to be spaced apart from each other in a vertical direction on the active region, a gate structure extending in a second direction to intersect the active region and the plurality of channel layers and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers, and a contact plug connected to the source/drain region. The source/drain region includes a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers, second epitaxial layers disposed on the first epitaxial layer, each including impurities in a first concentration, and doping layers stacked alternately with the second epitaxial layers, each including the impurities in a second concentration higher than the first concentration.

公开(公告)号：US11710796B2

公开(公告)日：2023-07-25

申请号：US17396059

申请日：2021-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Dongchan Suh ,  Jinbum Kim

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7854

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

公开(公告)号：US11264354B2

公开(公告)日：2022-03-01

申请号：US16869988

申请日：2020-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jungho Park ,  Dahye Kim ,  Minjun Bae

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

公开(公告)号：US11205649B2

公开(公告)日：2021-12-21

申请号：US16946060

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

公开(公告)号：US20210118877A1

公开(公告)日：2021-04-22

申请号：US16991530

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Dahye Kim ,  Jinbum Kim ,  Kyungin Choi ,  llgyou Shin ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

公开(公告)号：US12278271B2

公开(公告)日：2025-04-15

申请号：US17514379

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Jinbum Kim ,  Jaemun Kim ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/165 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a peripheral region, a first active pattern on the peripheral region, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns, which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, a first capping layer on the first active pattern, a second capping layer on the first capping layer, and a first gate insulating layer between the second capping layer and the first gate electrode. The first capping layer is between a sidewall of the first active pattern and the second capping layer. A concentration of germanium (Ge) of the first capping layer is greater than a concentration of germanium of the second capping layer.