公开(公告)号：US11062966B2

公开(公告)日：2021-07-13

申请号：US16357674

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Jae Lee ,  Sang-Lok Kim ,  Byung-Hoon Jeong ,  Tae-Sung Lee ,  Jeong-Don Ihm ,  Jae-Yong Jeong ,  Young-Don Choi

IPC: H01L21/26 ,  H01L21/66 ,  H01L23/528 ,  G01R31/3187

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US11024400B2

公开(公告)日：2021-06-01

申请号：US16862624

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/06

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10964360B2

公开(公告)日：2021-03-30

申请号：US16875163

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

公开(公告)号：US20200349986A1

公开(公告)日：2020-11-05

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10679717B2

公开(公告)日：2020-06-09

申请号：US16426391

申请日：2019-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/06

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10482935B2

公开(公告)日：2019-11-19

申请号：US15982431

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-june Park ,  Jeong-Don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/26 ,  H03K3/017 ,  H03K5/156

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US10171269B2

公开(公告)日：2019-01-01

申请号：US15099987

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo Lee ,  Jeong-Don Ihm ,  Anil Kavala ,  Byung-Hoon Jeong

IPC: H04L25/03 ,  H04L7/00 ,  H04L27/01

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

公开(公告)号：US20180350414A1

公开(公告)日：2018-12-06

申请号：US15982431

申请日：2018-05-17

Applicant: Samsung Electronics Co, Ltd

Inventor： Jung-june PARK ,  Jeong-Don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  H03K3/017 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2254 ,  H03K3/017 ,  H03K5/1565

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US20180336958A1

公开(公告)日：2018-11-22

申请号：US15977553

申请日：2018-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C29/02 ,  G11C5/06 ,  G11C7/10

CPC classification number: G11C29/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/06 ,  G11C16/102 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10014039B2

公开(公告)日：2018-07-03

申请号：US15333468

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo Lee ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Dae-Woon Kang

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/14 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.