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    POLAR CODE DECODING APPARATUS AND METHOD
    21.
    发明申请
    POLAR CODE DECODING APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20190140665A1

    公开(公告)日：2019-05-09

    申请号：US16013053

    申请日：2018-06-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Min SHIN ,  Min Uk KIM ,  Ki Jun LEE ,  Jun Jin KONG ,  Hong Rak SON

    IPC: H03M13/29 ,  H03M13/13

    Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

    NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME
    23.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME 审中-公开

    公开(公告)号：US20190065392A1

    公开(公告)日：2019-02-28

    申请号：US15684252

    申请日：2017-08-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Elona EREZ ,  Avner DOR ,  Moshe TWITTO ,  Jun Jin KONG

    IPC: G06F12/1009 ,  G06F12/02

    Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

    MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME
    24.
    发明申请
    MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME 审中-公开
    具有减少的存储器信道交换的存储器系统及其操作方法

    公开(公告)号：US20160321135A1

    公开(公告)日：2016-11-03

    申请号：US14699810

    申请日：2015-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Uri BEITLER ,  Jun Jin KONG

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/05

    CPC classification number: G06F11/1044 ,  G06F11/1012 ,  H03M13/05 ,  H03M13/611

    Abstract: A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.

    Abstract translation: 存储器件控制器包括纠错处理器和压缩处理器。 错误校正处理器被配置为获得通过存储器通道从源存储器块接收的页面数据的错误位置信息。 压缩处理器被配置为压缩获得的错误位置信息，并且将压缩的错误位置信息输出到目标存储器块，而不需要通过同一存储器通道的页数据。

    MEMORY SYSTEMS HAVING IMPROVED OUT-OF-ORDER EXECUTION OF COMMANDS AND METHODS FOR OPERATING THE SAME
    25.
    发明申请
    MEMORY SYSTEMS HAVING IMPROVED OUT-OF-ORDER EXECUTION OF COMMANDS AND METHODS FOR OPERATING THE SAME 有权
    具有改进的命令执行不足的记忆系统及其操作方法

    公开(公告)号：US20160306547A1

    公开(公告)日：2016-10-20

    申请号：US14686391

    申请日：2015-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amitai PERLSTEIN ,  Amir BENNATAN ,  Hanan LECHTMAN ,  Jun Jin KONG ,  Michael ERLIHSON

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

    Abstract: A memory device controller includes a main processor and a sequencer. The sequencer is configured to: estimate a time interval required to complete execution of a set of atom commands allocated to a channel of a non-volatile memory; calculate, for each of the plurality of atom commands, an urgency value associated with completing execution of a corresponding memory command after expiration of the time interval required to complete execution of the set of atom commands allocated to the channel; schedule each of the plurality of atom commands in the set of atom commands for execution by the non-volatile memory based on the calculated urgency values; and output the plurality of atom commands to the non-volatile memory for execution in the scheduled order.

    Abstract translation: 存储器件控制器包括主处理器和定序器。 定序器被配置为：估计完成执行分配给非易失性存储器的通道的一组原子命令所需的时间间隔; 对于所述多个原子命令中的每一个计算与完成执行分配给所述通道的所述原子命令集合所需的时间间隔期满之后完成对应的存储器命令的执行相关联的紧急度值; 基于所计算出的紧急度，安排所述原子命令集中的所述多个原子命令中的每一个，以由所述非易失性存储器执行; 并将多个原子命令输出到非易失性存储器，以按预定顺序执行。

    METHODS AND SYSTEMS FOR SOFT-DECISION DECODING
    26.
    发明申请
    METHODS AND SYSTEMS FOR SOFT-DECISION DECODING 有权
    软决策解码的方法和系统

    公开(公告)号：US20160301429A1

    公开(公告)日：2016-10-13

    申请号：US14683656

    申请日：2015-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yaron SHANY ,  Jun Jin KONG

    IPC: H03M13/45 ,  G11C29/52 ,  H03M13/15 ,  G06F11/10

    CPC classification number: H03M13/152 ,  H03M13/1515 ,  H03M13/1525 ,  H03M13/153 ,  H03M13/3707 ,  H03M13/451

    Abstract: At least one example embodiment discloses a method of soft-decision Wu decoding a code, the code being one of a generalized Reed-Solomon type and an alternant type. The method includes obtaining a module of the code, the module being a sub-module of at least a first extension module and a second extension module, the first extension module being defined by a set of first type constraints and the second extension module being defined by a set of second type constraints, the first type constraints being applicable to a first interpolation algorithm and a second interpolation algorithm and the second type constraints being applicable to the first interpolation algorithm, determining a basis for the first extension module and converting the basis for the first extension module to a basis for the module.

    Abstract translation: 至少一个示例性实施例公开了一种软判决吴解码码的方法，该代码是广义里德 - 所罗门类型和交替类型之一。 该方法包括获得代码的模块，模块是至少第一扩展模块和第二扩展模块的子模块，第一扩展模块由一组第一类型约束定义，第二扩展模块被定义 通过一组第二类型约束，第一类型约束适用于第一插值算法和第二插值算法，第二类型约束适用于第一插值算法，确定第一扩展模块的基础并将 第一个扩展模块为模块的基础。

    MEMORY CONTROLLER AND OPERATION METHOD THEREOF
    27.
    发明申请
    MEMORY CONTROLLER AND OPERATION METHOD THEREOF 审中-公开
    内存控制器及其操作方法

    公开(公告)号：US20130227213A1

    公开(公告)日：2013-08-29

    申请号：US13778396

    申请日：2013-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seong Hyeog CHOI ,  Jun Jin KONG ,  Jin Yeong KIM ,  Hong Rak SON ,  Yu Hun JEON

    IPC: G06F5/08

    CPC classification number: G06F5/08 ,  H04L9/0662

    Abstract: A memory controller and an operation method thereof are provided. The operation method includes storing a plurality of random sequences, selecting at least one random sequence among the plurality of random sequences according to a data pattern of a data block, and performing conversion by at least one of randomizing the data block using the selected at least one random sequence and derandomizing the randomized data block using the selected at least one random sequence.

    Abstract translation: 提供了一种存储器控制器及其操作方法。 操作方法包括存储多个随机序列，根据数据块的数据模式选择多个随机序列中的至少一个随机序列，并通过使用所选择的至少一个随机数据块中的至少一个进行转换 一个随机序列，并使用所选择的至少一个随机序列去随机化数据块。

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    29.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190340067A1

    公开(公告)日：2019-11-07

    申请号：US16217249

    申请日：2018-12-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DAE-HYUN KIM ,  Yong-Gyu CHU ,  Jun Jin KONG ,  Ki-Jun LEE ,  Myung-Kyu LEE

    IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  H01L25/065 ,  G11C11/401

    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

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