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    DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME
    21.
    发明公开
    DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20240364351A1

    公开(公告)日：2024-10-31

    申请号：US18765582

    申请日：2024-07-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsun Lee ,  Jaewoo Park ,  Myoungbo Kwak ,  Jinook Jung ,  Junghwan Choi

    IPC: H03L7/093 ,  H03L7/081 ,  H03L7/099

    CPC classification number: H03L7/093 ,  H03L7/0818 ,  H03L7/0991

    Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.

    Receiver including offset compensation circuit
    24.
    发明授权
    Receiver including offset compensation circuit 有权

    公开(公告)号：US11817861B2

    公开(公告)日：2023-11-14

    申请号：US17898631

    申请日：2022-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Seungjin Park ,  Jihwan Hyun ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03K5/00 ,  H03K5/01 ,  H03K5/003 ,  H03K5/24 ,  H03K5/05

    CPC classification number: H03K5/01 ,  H03K5/003 ,  H03K5/05 ,  H03K5/24

    Abstract: A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

    Apparatuses and methods for timing skew calibration
    25.
    发明授权
    Apparatuses and methods for timing skew calibration 有权

    公开(公告)号：US12235672B2

    公开(公告)日：2025-02-25

    申请号：US18363906

    申请日：2023-08-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung Maeng ,  Jaewoo Park ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: G06F1/10

    Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.

    Low dropout regulator and memory device including the same
    26.
    发明授权
    Low dropout regulator and memory device including the same 有权

    公开(公告)号：US11940830B2

    公开(公告)日：2024-03-26

    申请号：US17709853

    申请日：2022-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinook Jung ,  Jaewoo Park ,  Junhan Choi ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: G11C11/4074 ,  G05F1/575 ,  G11C11/4076 ,  G11C11/4093

    CPC classification number: G05F1/575 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093

    Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

    High resolution phase correcting circuit and phase interpolating device
    27.
    发明授权
    High resolution phase correcting circuit and phase interpolating device 有权

    公开(公告)号：US11888486B2

    公开(公告)日：2024-01-30

    申请号：US17872527

    申请日：2022-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinook Jung ,  Jaewoo Park ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03K5/00 ,  H03K5/01 ,  H03H11/16

    CPC classification number: H03K5/01 ,  H03H11/16 ,  H03K2005/00019

    Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

    Voltage regulator and semiconductor memory device having the same
    28.
    发明授权
    Voltage regulator and semiconductor memory device having the same 有权

    公开(公告)号：US11797038B2

    公开(公告)日：2023-10-24

    申请号：US17577201

    申请日：2022-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woochul Jung ,  Myoungbo Kwak ,  Jaewoo Park ,  Eunseok Shin ,  Junhan Choi

    IPC: G11C8/10 ,  G05F1/575 ,  G11C8/18 ,  G11C5/14

    CPC classification number: G05F1/575 ,  G11C5/147 ,  G11C8/10 ,  G11C8/18

    Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

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