公开(公告)号：US20220384476A1

公开(公告)日：2022-12-01

申请号：US17563547

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung KIM ,  Bumkyu KANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers . Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.

公开(公告)号：US20250056806A1

公开(公告)日：2025-02-13

申请号：US18610514

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Bumkyu KANG ,  Junyong PARK ,  Sukkang SUNG

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device and a data storage system are provided. The semiconductor device includes a peripheral circuit structure; a stack structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating through the stack structure. The stack structure includes a plurality of blocks spaced apart from each other by a first portion of the separation structure, each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, and the plurality of blocks include first blocks and a plurality of capacitor blocks disposed between first blocks adjacent to each other among the first blocks.

公开(公告)号：US20240405091A1

公开(公告)日：2024-12-05

申请号：US18541229

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a gate stacking structure including alternating gate electrodes and insulation layers on an insulation portion, a channel structure crossing the insulation portion and extending through the gate stacking structure, and a horizontal conductive layer connected to the channel structure between the insulation portion and the gate stacking structure, the horizontal conductive layer including a doped monocrystalline semiconductor layer having a dopant.

公开(公告)号：US20240347490A1

公开(公告)日：2024-10-17

申请号：US18751563

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon KIM ,  Sungmin HWANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.

公开(公告)号：US20240315034A1

公开(公告)日：2024-09-19

申请号：US18507258

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek JUNG ,  Sukkang SUNG

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a substrate, stacking structure, first selection gate electrode, memory gate electrodes stacked on the substrate; a first channel structure penetrating the stacking structure and extending along one direction, a first channel layer, a first dielectric layer between the first channel layer and stacking structure, a channel pad on the first channel layer; an insulation pattern above the stacking structure, a penetration portion exposing some of the first channel structure, a second selection gate electrode on the insulation pattern, a second channel structure extending in one direction penetrating the second selection gate electrode, a contact pattern connected to the first channel structure including a first portion within the penetration portion on an upper surface of the channel pad, and a second portion protruding toward the substrate to include a recess in the channel pad and the first dielectric layer inside a bottom surface of the first portion.

公开(公告)号：US20240178168A1

公开(公告)日：2024-05-30

申请号：US18237962

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho KIM ,  Woosung YANG ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H10B41/50 ,  H10B43/50

CPC classification number: H01L24/08 ,  H10B41/50 ,  H10B43/50 ,  H01L2224/08145

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first metal bonding layers on the first interconnection structure; and a second substrate structure connected to the first substrate structure, and the second substrate structure includes: a plating layer; gate electrodes stacked and spaced apart from each other in a first direction below the plating layer; channel structures penetrating through the gate electrodes and extending in the first direction; a separation region penetrating through the gate electrodes and extending in a second direction; a second interconnection structure below the gate electrodes and the channel structures; second metal bonding layers below the second interconnection structure and connected to the first metal bonding layers; and dummy pattern layers between the second metal bonding layers, extending in the second direction, and including an insulating material.

公开(公告)号：US20240038660A1

公开(公告)日：2024-02-01

申请号：US18197283

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Jaeho KIM ,  Sukkang SUNG

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/0652

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region. A memory stack includes a plurality of word lines extending in the memory cell region and the connection region in a horizontal direction that is parallel with an upper surface of the substrate. The plurality of word lines overlaps with each other in a vertical direction. A support is in the connection region and positioned at a side of the memory stack. The support includes a plurality of steps. A plurality of pad parts is on a top surface of the support. A plurality of contact plugs passes through at least some of the plurality of word lines in the vertical direction. The plurality of contact plugs directly contacts the plurality of pad parts for electrical connection therewith.

公开(公告)号：US20230378083A1

公开(公告)日：2023-11-23

申请号：US18172534

申请日：2023-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.

公开(公告)号：US20230012115A1

公开(公告)日：2023-01-12

申请号：US17570874

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho KIM ,  Jiwon KIM ,  Joonsung KIM ,  Sukkang SUNG ,  Sangdon LEE ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

公开(公告)号：US20220122933A1

公开(公告)日：2022-04-21

申请号：US17460873

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.