公开(公告)号：US11929366B2

公开(公告)日：2024-03-12

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0673

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US11631769B2

公开(公告)日：2023-04-18

申请号：US17321960

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Wandon Kim ,  Heonbok Lee ,  Yoontae Hwang

IPC: H01L29/78 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

公开(公告)号：US20230011088A1

公开(公告)日：2023-01-12

申请号：US17705343

申请日：2022-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Rakhwan Kim ,  Wandon Kim ,  Sunyoung Noh ,  Hanmin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

公开(公告)号：US11239334B2

公开(公告)日：2022-02-01

申请号：US16811605

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae Hwang ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US11145738B2

公开(公告)日：2021-10-12

申请号：US16886881

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Byounghoon Lee ,  Seungkeun Cha ,  Wandon Kim

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

公开(公告)号：US20210057533A1

公开(公告)日：2021-02-25

申请号：US16811605

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae HWANG ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45 ,  H01L29/08 ,  H01L21/285

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US20210035989A1

公开(公告)日：2021-02-04

申请号：US16780006

申请日：2020-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H01L27/1159 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US10811505B2

公开(公告)日：2020-10-20

申请号：US15990983

申请日：2018-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghan Lee ,  Wandon Kim ,  Jaeyeol Song ,  Jeonghyuk Yim ,  HyungSuk Jung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US09627509B2

公开(公告)日：2017-04-18

申请号：US14802519

申请日：2015-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbum Koo ,  Wandon Kim ,  Sangjin Hyun ,  Shinhye Kim ,  TaekSoo Jeon ,  Byung-Suk Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02362 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/51 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/78 ,  H01L2029/7858

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device.

公开(公告)号：US09093460B2

公开(公告)日：2015-07-28

申请号：US14022865

申请日：2013-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomseok Kim ,  Ohseong Kwon ,  Wandon Kim ,  Jaewan Chang ,  Kyuho Cho

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/75 ,  H01L28/91

Abstract: The present inventive concept provides semiconductor devices that may include a capacitor including a lower electrode, a dielectric layer, and an upper electrode which are sequentially stacked. An electrode-protecting layer may be provided on the capacitor. The upper electrode may include a conductive metal oxide and the electrode-protecting layer may include a sacrificial reaction layer including a metal-hydrogen compound.

Abstract translation: 本发明构思提供半导体器件，其可以包括依次层叠的包括下电极，电介质层和上电极的电容器。 可以在电容器上设置电极保护层。 上电极可以包括导电金属氧化物，并且电极保护层可以包括包含金属 - 氢化合物的牺牲反应层。