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    Techniques for reducing memory write operations using coalescing memory buffers and difference information
    21.
    发明授权
    Techniques for reducing memory write operations using coalescing memory buffers and difference information 有权

    公开(公告)号：US10732857B2

    公开(公告)日：2020-08-04

    申请号：US15611062

    申请日：2017-06-01

    Applicant: Seagate Technology LLC

    Inventor： Radoslav Danilak

    IPC: G06F3/06 ,  G06F12/02 ,  G11C16/34

    Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from a write operation. The method further comprises populating at least one coalescing memory buffer with difference information associated with the difference and to be used to update an associated block of the storage device.

    ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE
    23.
    发明申请
    ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE 审中-公开
    用于基于闪存存储器的数据存储的自适应ECC技术

    公开(公告)号：US20160188405A1

    公开(公告)日：2016-06-30

    申请号：US14945276

    申请日：2015-11-18

    Applicant: Seagate Technology LLC

    Inventor： Yan Li ,  Hao Zhong ,  Radoslav Danilak ,  Earl T Cohen

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G11C11/56

    CPC classification number: G06F11/1068 ,  G06F11/1016 ,  G06F11/1048 ,  G11C11/5628 ,  G11C29/52 ,  H03M13/05 ,  H03M13/2906

    Abstract: Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.

    Abstract translation: 与闪存一起使用的自适应ECC技术可以改善闪存的使用寿命，可靠性，性能和/或存储容量。 这些技术包括具有各种码率和/或各种码长（提供不同的纠错能力）的ECC方案和错误统计收集/跟踪（例如经由专用的硬件逻辑块）。 所述技术还包括根据ECC方案中的一个或多个的编码/解码，以及至少部分地基于来自错误统计收集/跟踪的信息（例如，经由 硬件逻辑自适应编解码器，从专用误差统计收集/跟踪硬件逻辑块接收输入）。 这些技术还包括随着时间的推移，以各种操作模式（例如，作为MLC页面或SLC页面）选择性地操作闪速存储器的一部分（例如，页面，块）。

    TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION
    24.
    发明申请
    TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION 审中-公开
    使用COALESCING MEMORY BUFFERS和差异信息减少内存写入操作的技术

    公开(公告)号：US20160011800A1

    公开(公告)日：2016-01-14

    申请号：US14862241

    申请日：2015-09-23

    Applicant: Seagate Technology LLC

    Inventor： Radoslav Danilak

    IPC: G06F3/06

    CPC classification number: G06F3/0616 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G11C16/349 ,  G11C16/3495

    Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from the write operation. The method further comprises populating at least one of one or more coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks. Additionally, the method comprises selectively writing the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers. The coalescing memory buffers are separate from the storage devices.

    Abstract translation: 本公开涉及使用聚结存储器缓冲器来减少存储器写入操作的示例。 在根据本公开的方面的一个示例实现中，一种方法包括计算要向其写入数据的存储设备的至少一个块的数据的当前状态与由写入操作产生的状态之间的差异 。 该方法还包括用与该差异相关联的差异信息填充一个或多个聚结存储器缓冲器中的至少一个，并且用于更新相关联的一个块。 另外，该方法包括基于确定合并存储器缓冲器的丰满度来将存储器中的差分信息选择性地写入到存储设备中。 合并存储缓冲区与存储设备分开。

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