公开(公告)号：US10229052B2

公开(公告)日：2019-03-12

申请号：US15609198

申请日：2017-05-31

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa ,  Ryan J. Goss ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.

公开(公告)号：US10090067B1

公开(公告)日：2018-10-02

申请号：US15608100

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Mark Ish ,  David S. Ebsen

IPC: G11C29/00 ,  G11C11/406 ,  G06F12/02 ,  G11C7/18 ,  G11C8/14

Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.

公开(公告)号：US20180173658A1

公开(公告)日：2018-06-21

申请号：US15899910

申请日：2018-02-20

Applicant: Seagate Technology LLC

Inventor： Ramdas Kachare ,  Timothy Canepa

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/1605 ,  G06F13/4022 ,  G06F13/4282

Abstract: An apparatus to arbitrate data transfer between a computing host and a storage device across an interface includes a data transfer limiter configured to track an amount of data credits used by a data transfer across the interface and an amount of accrued data credits available to the interface. The apparatus further includes a data transfer arbiter configured to selectively disable the data transfer across the interface when the amount of data credits used by the data transfer across the interface exceeds a first threshold, and to selectively enable the data transfer across the interface when the amount of data credits used by the data transfer across the interface does not exceed a second threshold. The amount of accrued data credits reduces the amount of data credits used by the data transfer.

公开(公告)号：US20180046543A1

公开(公告)日：2018-02-15

申请号：US15232058

申请日：2016-08-09

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F11/10 ,  H03M13/15 ,  G11C16/22 ,  G11C29/52 ,  G11C11/56 ,  G11C16/14

CPC classification number: G06F11/1072 ,  G06F2212/7207 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/22 ,  G11C29/52 ,  G11C2211/5641 ,  H03M13/11 ,  H03M13/154

Abstract: Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.

公开(公告)号：US09881682B1

公开(公告)日：2018-01-30

申请号：US15360821

申请日：2016-11-23

Applicant: Seagate Technology LLC

Inventor： Alex Tang ,  Timothy Canepa ,  Ramdas Kachare

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3495

Abstract: Embodiments described herein provide for linking retention parameters that affect data retention in flash to data stored in the flash. One embodiment includes a flash memory and a controller. The controller receives a plurality of write requests from a host, and stores data for the write request in flash pages of the flash memory along with indicators. The controller identifies at least one retention parameter that affects data retention of the stored data, and adds one or more of the indicators to an entry in a journal along with the at least one retention parameter. In response to determining that a data refresh is warranted based on the at least one retention parameter, the controller identifies the one or more indicators associated with the at least one retention parameter in the entry, locates the stored data corresponding to the one or more indicators, and refreshes the stored data.

公开(公告)号：US09684613B2

公开(公告)日：2017-06-20

申请号：US14277920

申请日：2014-05-15

Applicant: Seagate Technology LLC

Inventor： Nital Patwa ,  Timothy Canepa ,  Yimin Chen

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2408 ,  Y02D10/14

Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.

公开(公告)号：US10756895B2

公开(公告)日：2020-08-25

申请号：US16165582

申请日：2018-10-19

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Timothy Canepa ,  Ramdas Kachare

IPC: G06F21/44 ,  H04L29/06 ,  H04L9/08 ,  H04L9/32 ,  G06F12/14

Abstract: Systems and methods for using encryption keys to manage data retention are described. In one embodiment, the systems and methods may include receiving data such as user data from a host of the storage drive, encrypting the data using an encryption key, writing the encrypted data to the storage drive, and retaining the encrypted data on the storage drive based at least in part on a validity of the encryption key.

公开(公告)号：US20190095341A1

公开(公告)日：2019-03-28

申请号：US16201733

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US20180351582A1

公开(公告)日：2018-12-06

申请号：US15610744

申请日：2017-06-01

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa

IPC: H03M13/35 ,  H03M13/00 ,  G06F3/06 ,  G06F12/02 ,  H03M13/11 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52

CPC classification number: H03M13/353 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0688 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7205 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/2906 ,  H03M13/6577

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.

公开(公告)号：US20180350447A1

公开(公告)日：2018-12-06

申请号：US15607784

申请日：2017-05-30

Applicant: Seagate Technology, LLC

Inventor： David S. Ebsen ,  Mark Ish ,  Timothy Canepa

IPC: G11C29/00 ,  G06F12/02 ,  G11C11/406 ,  G11C7/18 ,  G11C8/14 ,  G06F12/1045

CPC classification number: G11C29/789 ,  G06F12/0238 ,  G06F12/1054 ,  G06F12/1063 ,  G11C7/18 ,  G11C8/14 ,  G11C11/40607

Abstract: A data storage device may consist of a non-volatile memory connected to a selection module. The non-volatile memory can have a rewritable in-place memory cell that has a read-write asymmetry. The selection module can dedicate a portion of the non-volatile memory to a data map that can be self-contained along with reactively and proactively altered by the selection module.