公开(公告)号：US20170033233A1

公开(公告)日：2017-02-02

申请号：US15219396

申请日：2016-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichi KOEZUKA ,  Kenichi OKAZAKI ,  Masami JINTYOU ,  Takahiro IGUCHI ,  Naoto GOTO

IPC: H01L29/786 ,  H01L29/04 ,  H01L27/12 ,  G06F3/041 ,  H01L27/105 ,  H01L27/146 ,  C23C16/455 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/78606 ,  C23C14/08 ,  C23C14/086 ,  C23C14/3414 ,  G06F1/1643 ,  G06F1/169 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04102 ,  G06F2203/04103 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/14616 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: In a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The transistor includes an oxide semiconductor film over a first insulating film; a second insulating film over the oxide semiconductor film; a gate electrode over the second insulating film; a metal oxide film in contact with a side surface of the second insulating film; and a third insulating film over the oxide semiconductor film, the gate electrode, and the metal oxide film. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The source region and the drain region contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.

Abstract translation: 在包括氧化物半导体的晶体管中，抑制了电特性的变化，提高了可靠性。 晶体管包括在第一绝缘膜上的氧化物半导体膜; 氧化物半导体膜上的第二绝缘膜; 第二绝缘膜上的栅电极; 与所述第二绝缘膜的侧面接触的金属氧化物膜; 以及氧化物半导体膜上的第三绝缘膜，栅电极和金属氧化物膜。 氧化物半导体膜包括与栅电极重叠的沟道区域，与第三绝缘膜接触的源极区域和与第三绝缘膜接触的漏极区域。 源区和漏区含有氢，硼，碳，氮，氟，磷，硫，氯，钛和稀有气体中的一种或多种。

公开(公告)号：US20160225796A1

公开(公告)日：2016-08-04

申请号：US15075765

申请日：2016-03-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Takahiro SATO ,  Masami JINTYOU

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/041 ,  G06F2203/04103 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/7869

Abstract: A semiconductor device including a transistor and a connection portion is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film and at a position overlapping with the gate electrode, and source and drain electrodes electrically connected to the oxide semiconductor film; and the connection portion includes a first wiring on the same surface as a surface on which the gate electrode is formed, a second wiring on the same surface as a surface on which the source and drain electrodes are formed, and a third wiring connecting the first wiring and the second wiring. The distance between an upper end portion and a lower end portion of the second wiring is longer than the distance between an upper end portion and a lower end portion of each of the source and drain electrodes.

公开(公告)号：US20150316818A1

公开(公告)日：2015-11-05

申请号：US14678037

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami JINTYOU ,  Yamato AIHARA

IPC: G02F1/1335 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1368

CPC classification number: G02F1/133553 ,  G02F1/133345 ,  G02F1/133524 ,  G02F1/133555 ,  G02F1/1336 ,  G02F1/13439 ,  G02F1/1368 ,  H01L27/1225

Abstract: It is an object to provide a display device of which image display can be favorably recognized. Another object is to provide a manufacturing method of the display device with high productivity. Over a substrate, a pixel electrode that reflects incident light through a liquid crystal layer, a light-transmitting pixel electrode, and a structure whose side surface is covered with a reflective layer and which is positioned to overlap with the light-transmitting pixel electrode are provided. The structure is formed over a light-transmitting etching-stop layer, and the etching-stop layer remains below the structure as a light-transmitting layer.

Abstract translation: 本发明的目的是提供可以有利地识别图像显示的显示装置。 另一个目的是提供高生产率的显示装置的制造方法。 在基板上，反射通过液晶层的入射光的像素电极，透光像素电极和侧面被反射层覆盖并且与透光像素电极重叠的结构， 提供。 该结构形成在透光蚀刻停止层上，并且蚀刻停止层保持在作为透光层的结构的下方。

公开(公告)号：US20140306221A1

公开(公告)日：2014-10-16

申请号：US14247676

申请日：2014-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichi KOEZUKA ,  Yasutaka NAKAZAWA ,  Yukinori SHIMA ,  Masami JINTYOU ,  Masayuki SAKAKURA ,  Motoki NAKASHIMA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1229 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7869 ,  H01L29/78696

Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.

Abstract translation: 处理使用铜，铝，金，银，钼等形成的布线的步骤的稳定性增加。 此外，半导体膜中的杂质浓度降低。 此外，提高了半导体器件的电特性。 在包括氧化物半导体膜，与氧化物半导体膜接触的氧化物膜和与氧化膜接触并包括铜，铝，金，银，钼等的一对导电膜的晶体管中， 氧化物膜具有多个晶体部分，并且在晶体部分中具有c轴取向，并且c轴在与氧化物半导体膜或氧化物膜的顶表面的法向量平行的方向上排列。

公开(公告)号：US20250160123A1

公开(公告)日：2025-05-15

申请号：US18835069

申请日：2023-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuharu HOSAKA ,  Yukinori SHIMA ,  Masami JINTYOU ,  Masataka NAKADA ,  Junichi KOEZUKA ,  Kenichi OKAZAKI

IPC: H10K59/121 ,  H10K59/12

Abstract: A semiconductor device including a transistor having a minute size is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer including a region overlapping with the first conductive layer with the first insulating layer therebetween, a third conductive layer, and a third insulating layer. The second conductive layer and the first insulating layer have a first opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface and a side surface of the second conductive layer, a side surface of the first insulating layer, and a top surface of the first conductive layer. The third insulating layer is provided over the first insulating layer, the first semiconductor layer, and the second conductive layer. The third conductive layer is provided over the third insulating layer. The second insulating layer is provided over the third conductive layer and the third insulating layer.

公开(公告)号：US20250113716A1

公开(公告)日：2025-04-03

申请号：US18728173

申请日：2023-01-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuharu HOSAKA ,  Yukinori SHIMA ,  Masami JINTYOU ,  Masataka NAKADA ,  Junichi KOEZUKA ,  Kenichi OKAZAKI

IPC: H10K59/131 ,  H10K59/12

Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is provided over the first insulating layer and includes a second opening in a region overlapping with the first opening. The semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second insulating layer is provided over the semiconductor layer. The third conductive layer is provided over the second insulating layer. The first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer. The fourth insulating layer includes a region having a higher film density than the third insulating layer.

公开(公告)号：US20240136442A1

公开(公告)日：2024-04-25

申请号：US18378688

申请日：2023-10-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kenichi OKAZAKI ,  Masami JINTYOU ,  Kensuke YOSHIZUMI

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/7869 ,  H01L21/02274 ,  H01L21/2654 ,  H01L21/266

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided.
The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium. The first element exists in a state of being bonded to oxygen.

公开(公告)号：US20230320135A1

公开(公告)日：2023-10-05

申请号：US18127198

申请日：2023-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuharu HOSAKA ,  Masami JINTYOU ,  Takahiro IGUCHI ,  Chieko MISAMA ,  Ami SATO ,  Masayoshi DOBASHI

IPC: H10K59/121 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H10K59/1201

Abstract: Provided is a semiconductor device having a high degree of integration, which includes first and second transistors and a first insulating layer. The first transistor includes a first semiconductor layer, a second insulating layer, and first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and fourth to sixth conductive layers. The first insulating layer includes a region in contact with the first semiconductor layer and the first conductive layer and includes an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The second conductive layer is positioned over the first insulating layer. The third conductive layer is positioned over the first semiconductor layer and includes a region overlapping with the inner wall of the opening with the second insulating layer positioned therebetween. The second semiconductor layer is positioned over the first insulating layer and in contact with side and top surfaces of a side end portion of the fourth conductive layer and side and top surfaces of a side end portion of the fifth conductive layer; the side end portions face each other. The sixth conductive layer is positioned over the second semiconductor layer with the third insulating layer positioned therebetween. The first transistor is electrically connected to the second transistor.

公开(公告)号：US20230317857A1

公开(公告)日：2023-10-05

申请号：US18207176

申请日：2023-06-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC: H01L29/786 ,  H01L29/10 ,  H01L21/02 ,  H01L21/465 ,  H10K59/123 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/1033 ,  H01L29/786 ,  H01L21/02551 ,  H01L21/02554 ,  H01L29/78693 ,  H01L21/02422 ,  H01L21/02631 ,  H01L21/465 ,  H01L29/78603 ,  H10K59/123 ,  H01L29/78696 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/24 ,  H01L29/42356 ,  H01L21/02565 ,  H01L21/30604 ,  H01L27/1259 ,  H01L29/66742 ,  H01L29/66969

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

公开(公告)号：US20230020210A1

公开(公告)日：2023-01-19

申请号：US17949632

申请日：2022-09-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kenichi OKAZAKI ,  Masami JINTYOU ,  Takahiro IGUCHI ,  Yukinori SHIMA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/32 ,  H01L27/15

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer containing a metal oxide, a first insulating layer, a second insulating layer, a third insulating layer containing a nitride, and a first conductive layer. The first insulating layer includes a projecting first region that overlaps with the semiconductor layer and a second region that does not overlap with the semiconductor layer and is thinner than the first region. The second insulating layer is provided to cover a top surface of the second region, a side surface of the first region, and the semiconductor layer. The first conductive layer is provided over the second insulating layer and a bottom surface of the first conductive layer over the second region includes a portion positioned below a bottom surface of the semiconductor layer.